TIP810 Version 3.0 User Manual Issue 3.0.4
Page 13 of 19
5.2 "PeliCAN"-Mode Register Set
The complete SJA1000 “PeliCAN" mode register set is accessible in the
IP Memory Space.
(Only the
lower 32bytes of the "PeliCAN"-Mode register set are accessible in IP I/O Space.) All registers are
byte sized. Read accesses to write-only registers will result in a value of 0xFF on the data bus.
Register (function in Operating/Reset Mode)
Address
Access
Mode Register (mode/mode)
0x01
R/W
Command Register
0x03
W
Status Register (status/status)
0x05
R
Interrupt Register (interrupt/interrupt)
0x07
R
Interrupt Enable Register (interrupt enable/interrupt enable)
0x09
R/W
Reserved (0x00/0x00)
0x0B
R
Bus Timing Register 0 (Bus Timing 0/Bus Timing 0)
0x0D
R/(W)
Bus Timing Register 1(Bus Timing 1/Bus Timing 1)
0x0F
R/(W)
Output Control Register (Output Control /Output Control)
0x11
R/(W)
Test Register
0x13
R
Reserved (0x00/0x00)
0x15
R
Arbitration Lost Capture Register (ALC/ALC)
0x17
R
Error Code Capture Register (ECC/ECC)
0x19
R
Error Warning Limit Register (EWL/EWL)
0x1B
R/(W)
RX Error Counter Register (RX Error Counter/RX Error Counter)
0x1D
R/(W)
TX Error Counter Register (TX Error Counter/TX Error Counter)
0x1F
R/(W)
TX,RX Frame information Register (TX,RX Frame information/
Acceptance Code)
0x21 R/W
TX,RX Identifier 1 Register (TX,RX Identifier 1/Acceptance Code 1)
0x23
R/W
TX,RX Identifier 2 Register (TX,RX Identifier 2/Acceptance Code 2)
0x25
R/W
TX,RX Identifier 3 Register (TX,RX Identifier 3/Acceptance Code 3)
0x27
R/W
TX,RX Identifier 4 Register (TX,RX Identifier 3/Acceptance Mask 0)
0x29
R/W
TX, RX Data 1 Register /Acceptance Mask 1
0x2B
R/W
TX, RX Data 2 Register /Acceptance Mask 2
0x2D
R/W
TX, RX Data 3 Register /Acceptance Mask 3
0x2F
R/W
TX, RX Data 4 Register /0x00
0x31
R/W
TX, RX Data 5 Register /0x00
0x33
R/W
TX, RX Data 6 Register /0x00
0x35
R/W
TX, RX Data 7 Register /0x00
0x37
R/W
TX, RX Data 8 Register /0x00
0x39
R/W
RX Message Counter Register (RX Message Counter/ RX Message
Counter)
0x3B R
RX Buffer Start Address Register (RX Buffer Start Address/ RX Buffer
Start Address)
0x3D R/W
Clock Divider Register (Clock Divider/ Clock Divider)
0x3F
R/W
Internal RAM address 0 (FIFO)
0x41
R/W
Internal RAM address 1 (FIFO)
0x43
R/W
Internal RAM address 2 (FIFO)
0x45
R/W
