VEEK-MT-SoCKit User Manual
March 17, 2014
12
Horizontal Valid
tHA
800
tCLK
Horizontal Blank
tHB
256
tCLK
Vertical Period
tV
525
tH
Vertical Valid
tVA
480
tH
Vertical Blank
tVB
45
tH
SYNC
HSYNC setup time
Thst
8
ns
HSYNC hold time
Thhd
8
ns
VSYNC Setup Time
Tvst
8
ns
VSYNC Hold Time
Tvhd
8
ns
Horizontal Period
th
1056
tCLK
Horizontal Pulse Width
thpw
30
tCLK
thb+thpw=46DCLK
is fixed
Horizontal Back Porch
thb
16
tCLK
Horizontal Front Porch
thfp
210
tCLK
Horizontal Valid
thd
800
tCLK
Vertical Period
tv
525
th
Vertical Pulse Width
tvpw
13
th
tvpw + tvb =
23th
is fixed
Vertical Back Porch
tvb
10
th
Vertical Front Porch
tvfp
22
th
Vertical Valid
tvd
480
th
DATA
Setup time
Tdsu
8
ns
Hold time
Tdsu
8
ns
Table 3-2 Pin Assignment of the LCD Touch Panel
Signal Name
FPGA Pin
No.
Description
I/O Standard
LCD_B0
C4
LCD blue data bus bit 0
2.5V
LCD_B1
D5
LCD blue data bus bit 1
2.5V
LCD_B2
A3
LCD blue data bus bit 2
2.5V
LCD_B3
A4
LCD blue data bus bit 3
2.5V
LCD_B4
E11
LCD blue data bus bit 4
2.5V
LCD_B5
F11
LCD blue data bus bit 5
2.5V
LCD_B6
F8
LCD blue data bus bit 6
2.5V
LCD_B7
F9
LCD blue data bus bit 7
2.5V
LCD_DCLK
E6
LCD Clock
2.5V
LCD_DE
C3
Data Enable signal
2.5V
LCD_DIM
F13
LCD backlight enable
2.5V
LCD_DITH
H8
Dithering setting
2.5V
LCD_G0
D12
LCD green data bus bit 0
2.5V