WL865E4-P Module Hardware User Guide
1VV0301580 Rev. 4
Page
22
of
56
2019-08-08
Power Up/Down Sequence
The RESET# is the main power disable/enable pin, including both the WIFI and BLE. All
supplies should be stable for a minimum of 10 µs before RESET# is de-asserted (that is,
when greater than VIL for VDD_VIO). If VDD_VIO = 3.3V, then VDD_BLE, VDD_WLAN,
and VDD_VIO can share same 3.3V power
Figure 2: WL865E4-P P on RESET
5.2.1.
Power-on reset timing
Parameter
Description
Min
Max Unit
T
R
Rise time of the power to 90% of final voltage
N/A
25
ms
T
S
Minimum time before RESET# is de-asserted
10
N/A
µs
Table 6: Wl865E4-P on Reset Table
Be sure that VDD_VIO will be powered before or at same time than
VDD_BLE and VDD_WLAN.
Either do a VDD_BLE and VDD_WLAN enable circuittry controlled by
VDD_VIO or guarantee that all 3 power nets are connected together
with bigger bypass capacitances at PAD VDD_BLE and VDD_WLAN.
Do to possible instant peak absorbtion, each of the 3 main Power nets
should be dimensioned for a 1A@3V3.
Unconditional Shutdown
Control the RESET# pin only in Open Drain configuration.
The RESET# is used for unconditional Hardware RESET.
RESET# pin has an internal PU of 120 KOhm resistor.
Make provisioning at RESET# pin of a 10 KOhm PU resistor to VDD_VIO. Initialy do NOT
MOUNT.
Содержание WL865E4-P
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