LE915Ax-P
Hardware Design Guide
1VV0301680 Rev. 2
Page 22 of 51
2021-10-04
Not Subject to NDA
Figure 3: Power off sequence
Communication Ports
5.2.1.
USB 2.0 Interface
The USB controller of LE915Ax-P is compliant with USB 2.0 specification and the data
rate up to 480Mbps. PCB routes must be designed so that USB lines are
90 Ohm
differential
.
Table 13
:
USB 2.0 interface
The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz, therefore the
signal traces should be carefully routed. Trace lengths, channel number and capacitive
loading should be minimized. The characteristic impedance value should be as close as
possible to the 90 Ohms differential.
ESD protection can be added to USB D+/D- lines in case of external connector for cable
connection.
Proper components for USB 2.0 must be used.
Warning: The
Maximum input voltage range of USB_EXT_VBUS_VLD
is up to 3.6V. It is required to have a non-inverting level shifter or
voltage divider to connect this port to an external 5.1V VBUS
.
Pin
Signal
I/O
Function description
56
USB_EXT_VBUS_VLD
I
1.8V logical input to detect VBUS
57
USB_D+
I/O USB 2.0 plus, differential
57
USB_D-
I/O
USB 2.0 minus, differential
Содержание LE915A P Series
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