Tektronix WFM 601A, Руководство по обслуживанию

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Block Diagram Descriptions
3–2
WFM 601A, WFM 601E, & WFM 601M Service Manual
to the jitter signal then sent to the positive and negative peak detectors. The DC
outputs of these detectors connect to the A/D converter. The unfiltered Jitter
signal is separately peak detected and the DC outputs connected to the A/D
converter. The Jitter circuit includes a switch that selects between the Jitter signal
and the sampled Eye signal for display.
The Signal Level Meter compares the amplitude of the serial digital signal at
10 MHz and 77 MHz. The amplitude at each of the frequencies is output as a
logarithmic DC voltage to the A/D converter. The microprocessor compares
these levels to determine the cable length measurement.
The Eye Pattern circuit is an equivalent-time sampler that allows viewing of the
serial bit stream as a voltage-versus-time signal. Using a phase locked oscillator,
the sample clock (6.75 MHz) is derived from the 27 MHz Parallel Clock and
horizontal line frequency (FH
)
signals. The input signal is displayed either with
serial receiver equalization (Eq Eye) or without (Eye).
The Coprocessor receives 10 bit parallel video input from the Deserializer, the
recovered 27 MHz clock, and control instructions from the microprocessor. The
coprocessor performs gamut and format error checking on the component video.
Three horizontal lines of the component video data are stored in a buffer RAM
for the Digital Data displays. The coprocessor outputs the clocks and 10 bit
interleaved video data to enable the recovery of the Y, R–Y and B–Y signals by
the Half Band filters and DACs. In addition, it generates the signals used for
clamping, to re-establish the vertical blanking interval, and to provide composite
synchronization. The coprocessor removes nonvideo data from the signal, such as
end of active video (EAV), start of active video (SAV), and ancillary data.
The Deserializer receives the 270 MHz component serial data and the recovered
parallel clock. The output is 10 bit video component data for the coprocessor.
The Phase Locked Loop circuit synchronizes an oscillator circuit with the
recovered 27 MHz clock. A switch circuit allows selection of the direct
recovered clock or the onboard 27 MHz clock, which appears as the front-panel
selection CONFIG–FORMAT–SYNC AFC.
The multiplexed video data stream from the coprocessor is converted to analog
components by three digital-to-analog converters (DACs). The Y Delay circuit
delays the luminance data to ensure it passes through the Half Band filter and
DAC properly synchronized with the chrominance signals. The coprocessor
generates the clock and timing enable signals for the luminance and two color
difference Half Band filters and DACs.
Signal Level Meter
Eye Pattern Sampler
Coprocessor
Deserializer
Phase Locked Loop and
Clock Regenerator
Y Delay, Half-Band Filters,
and DACs