Tektronix WFM 601A, Руководство по обслуживанию

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WFM 601A, WFM 601E, & WFM 601M Service Manual
3–1
Block Diagram Descriptions
This section provides a circuit description based on the three block diagrams, at
the front of Diagrams, section 9. This section also describes the Power Supply
based on the major blocks on the A1 Power Supply schematics, also in section 9.
Block Diagram 1, Input and Waveform Display
Block diagram 1 contains the serial inputs and outputs, Eye pattern sampler,
vertical and horizontal amplifiers, the CRT, and blanking.
The serial inputs are 75
W
compensated (externally terminated) passive loop-
through inputs. Input transistors and capacitive coupling buffer the input signals
to keep return loss constant up through 300 MHz. Discreet components select the
SER A or SER B input. The switch and amplifier provide a gain of 0.5 to
connectors J1 and J2.
The Serial Out, MON OUT, and Jitter Out signals pass straight through the A4
board. The EXT REF input is a 75
W
compensated, high impedance loop-through
input.
The component serial digital video signal is buffered and applied to the Serial
Receiver circuit. An unbuffered version of the digital signal is routed to the Eye
Sampler circuit. The Serial Receiver contains a phase-locked loop circuit that
locks its clock to the incoming 270 MHz data signal. Jumper P13 is normally on
pins 2 and 3, which selects a clock adjust circuit that brings the oscillator close to
the incoming frequency so the PLL can operate. With P13 on pins 1 and 2, you
can adjust R269 to change the oscillator center frequency. If you remove cable J3
from the DAC board for troubleshooting, you can move P13 to pins 1 and 2 and
adjust R269 to lock on the incoming signal.
If the input signal amplitude is low, the Serial Receiver provides equalization by
boosting the high-frequency components of the signal. A Cable Driver circuit
buffers the reclocked serial digital signal for the Serial Out rear-panel output. A
divide by 10 circuit provides the 27 MHz clock for the Eye pattern circuit. An
A/D converter digitizes various analog inputs under microprocessor control.
The Jitter Demodulator is a phase detector that receives a reference clock and the
27 MHz clock derived from the input signal. The output is a Jitter signal for
display, measurement, and export to the rear panel Jitter output. The Peak
Detector circuit splits the incoming Jitter signal into two paths: the high-pass
peak detector and the raw peak detector. The selected high-pass filter is applied
Input Switching and
Outputs
Serial Receiver
Jitter Demodulator and
Peak Detectors