External Controllers and Printers
6–10
ST112 SONET Transmission Test Set
Specific Command Implementations
Reset Command
, as defined in the ANSI IEEE 488.2-1987 standard, the Test Set reset command
(*rst) does the following:
•
Resets all device settings to their default values, except remote interface settings.
•
Ignores macros (macros are not implemented in the Test Set).
•
Forces the Test Set into the Operation Complete Command Idle State (OCIS) and Operation
Complete Query Idle State (OQIS).
Overlapped and Sequential Commands
: All Test Set commands are sequential.
Operation Complete Message
: Test Set command operation is always immediate.
GPIB Status and Event Reporting System
The
ST112 SONET Transmission Test Set
GPIB status and event reporting functions are
compatible with the ANSI IEEE 488.2-1987 standard. The status and event reporting system can
be configured to alert the GPIB controller whenever a status change or event occurs. This is
accomplished by maintaining two status registers and their associated enable register. The four
status registers are:
•
Standard Event Status Register (SESR) general purpose status register
•
Event Status Enable Register (ESER) enable register
•
Status Byte Register (SBR) general purpose status register
•
Service Request Enable Register (SRER) enable register
The GPIB bus SRQ (service request) line is asserted when one or more status bits are set. The
controller uses a serial poll procedure to find out which instrument initiated the SRQ. Specific
status bits can be enabled or disabled to control which status changes or events result in an SRQ.
The Test Set status registers can be read and set from the RS-232 control interface, however, the
SRQ function is only available on the GPIB bus.
A status register may contain defined (used) bits and undefined (unused) bits. Each defined bit in
a status register corresponds to a given instrument status or event. Once cleared (set to zero), the
value of a status bit will remain zero (false) as long as the corresponding event or status does not
occur. However, if it is enabled, the value of a status bit will be set to one (true) when the
corresponding event or status occurs. Status bits are latched once a status bit is set to one and
will remain in this state even when the corresponding event or status becomes false, until the bit
is reset by a command or when the
ST112 SONET Transmission Test Set
is powered off.
Each status register has an associated enable register. Moreover, each defined bit in a status
register has a corresponding defined bit in the associated enable register. When an enable bit is
set to zero, then the corresponding status bit is ignored by the instrument regardless of the state
of the relevant event or instrument status. However when an enable bit is set to one, the
corresponding status bit is enabled.
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