Tektronix 1740A Series, Руководство пользователя

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Circuit Theory
1740A/1750A/1760 – Series Service Manual
3–25
The transitions from the 50% point detector are one input to a one shot, U12A.
The other input is the sync gate from the Line Rate Controller. When the 50%
transition occurs during sync time (active video line), U12A switches and
generates a pulse whose duration is dependent on the current through Q15. Q15
is controlled by a DAC level from the Vector board (Diagram 13). The trailing
edge of the pulse output by U12A triggers U12B, another one shot, whose output
is a 126-ns pulse. When this pulse straddles a zero crossing of subcarrier the
charge pump detector outputs a dc level.
The phase-shifted differential F
SC
signal, output by U9, is fed to a phase
detector, U23D. U23, Q19, and Q20 form the charge pump phase detector. The
phase detector is gated on with a sample pulse from U12B. During the time the
phase detector is gated on, current flows in and out of the integrating capacitors,
C70 and C71. The direction of the current flow is controlled by the F
SC
feedback signal driving U23D pins 2 and 4. When pin 2 is low and pin 4 is high,
current flows out of the integrating capacitors through the collector of U23D (pin
5). When pin 2 is high and pin 4 is low, the current from U23 is routed into a
current mirror (Q19 and Q20) and added to the integrating capacitors. An
equilibrium condition exists when the net charge transfer is zero; therefore, the
transitions at pin 2 will occur at the mid point of the 126-ns pulse from U12B
when the loop is locked. R122 and the integrating capacitors, C70 and C71,
form the loop filter that controls the phase lock loop response. The net current
flow into the loop filter produces the VCO control voltage, which controls the
varactor, CR10, through R96.
The lock detector is made up of U14A and U28. When lock is achieved the
output of U28 is high, which has the gate of Q26 high and keeps it turned off. In
addition, the output of U28 is the SCH locked level (high for locked and low for
unlocked) that is detected by the SCH lock detector on Diagram 13. When the
charge pump detector outputs a sawtooth waveform, the output of U28 goes low
and turns on Q26, which connects the –8 V supply directly to R153 to boost the
current through the charge pump detector to speed lockup. In addition to
speeding up the detector, the SCH Locked line goes low, causing the SCH lock
detector on Diagram 13 to output a low to the Microprocessor.
U9 is a Programmable Array Logic (PAL) device. It contains all of the logic
required to output a signal that can be converted to an analog sync coincident
sine wave for plotting against the burst locked sine wave in a vector-type display.
The resultant difference is the horizontal-to-subcarrier phase error.
Sync Delay
Charge Pump Comparator
Lock Detector
4 F
SC
Divider
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