Tektronix 1740A Series, Руководство пользователя

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Circuit Theory
1740A/1750A/1760 – Series Service Manual
3–15
Flash EPROM output is written into the Random Access Memory (RAM), U11
& U17, when SRAM and WR LO and WR HI are pulled low. The Microproces-
sor reads the RAM when SRAM and RD LO and RD HI are pulled low.
The Address Decoder is U21. It is a 3-line to 8-line decoder using the 3 MSBs
of the address bus to output 5 control signals. The decoder is enabled when the
Microprocessor pulls DECODE and ADDR EN low.
U2 is a logic array that decodes Microprocessor outputs. It uses buffered address
0 (BA0) as a clock. Its outputs enable the data and address buffers, control read
and write for the RAM and Flash EPROM, and output 2 control signals for
digital expansion.
U23 buffers 5 outputs and 1 input for the Microprocessor. It is permanently
enabled by pulling pins 1G and 2G low. 2G is set up to be pulled low when a
component (1760–Series) board is installed.
Diagram
7
Dynamic Control
Microprocessor instructions are synchronized to line and field rates to generate
time dependent control signals by the circuitry on this diagram.
The sync separator consists of U68 and U71. The V sync and H sync outputs are
used to synchronize the Line Rate Controller (U34). The two integrated circuits
are identical, one is driven by the internal video that drives the vertical deflection
circuits and the other is driven by the selected reference input.
The Line Rate Controller (U34) is a programmable logic device. It is capable of
logic and timing simulations. It has three separate clock signals; 6 MHz from
U93, 16 MHz from the Microprocessor, and a 5 MHz clock signal from an ECL
oscillator. In order to lock the internal clock to video, U34 asserts START at the
leading edge of H sync. When START goes low, it remains low for approxi-
mately 60
m
s; it then goes high to shut off the oscillator (Q4, Q5, Q6, and U26C)
until the next cycle.
U34 has 144 configurable blocks of RAM that are loaded from ROM at power
up. U40 is a first-in/first-out RAM that is loaded from the Microprocessor, and
read out to the Line Rate Controller and synchronous latches on command from
the Line Rate Controller. U40 can be written to by the Microprocessor and read
from by the Line Rate Controller independently.
Decoders
Buffered Output
Sync Separator
Line Rate Controller
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