Block Diagram Description
1740A/1750A/1760 – Series Service Manual
3–3
An offset voltage from the DACs vertically positions the display. When CRT
readout is being processed the gain of the amplifier is changed by the Line Rate
Controller. The differential output of the Vertical Amplifier drives the vertical
output amplifier to normalize signal amplitude and drive the CRT deflection
plates.
An additional internal amplifier stage provides a chrominance differential output
to drive the vector chroma amplifier. Gain of the chrominance signal is
controlled by the Microprocessor.
Line and Field Rate signal generators are started and stopped by the retrace
signals from the Line Rate Controller. Sweep ramp run up times
17 ms for the
field sweep and 64
m
s for the line sweep are controlled by the Microprocessor.
The Horizontal Signal Multiplexer is controlled by the Line Rate Controller to
select a signal to drive the horizontal circuitry. The vectorscope B–Y and the
component horizontal signal outputs are input through this multiplexer.
The Horizontal Amplifier is a variable gain amplifier with controlling inputs
from either the Microprocessor or the Line Rate Controller. Stage gain is
controlled by the microprocessor-generated control voltages. Magnification is
switched by a signal from the Line Rate Controller.
An offset voltage horizontally positions the display. The amount of positioning
offset required for the Waveform mode is significantly greater than that required
for the other display modes; therefore, a separate offset is required. When CRT
readout is being processed the gain of the amplifier is changed by the Readout
Select signal from the Line Rate Controller.
The differential output of the Horizontal Amplifier drives the horizontal output
amplifier to normalize signal amplitude and drive the CRT deflection plates.
An additional amplifier stage within the Horizontal Amplifier provides a
differential output that controls the intensity for the Picture Monitor mode.
Picture Monitor contrast is controlled by the Microprocessor.
The Blanking Logic is a multiplexer that is controlled by the Line Rate
Controller. It selects the blanking/unblanking signals that drive the Z–Axis
Amplifier, which drives the CRT control grid.
Sweep Generators and
Horizontal Signal
Multiplexer
Horizontal Amplifier
Blanking Logic
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Содержание 1740A Series
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