TechNexion PICO-IMX6UL-EMMC, Руководство по оборудованию

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PICO-IMX6UL-EMMC REV. A1. HARDWARE MANUAL
– VER 1.00 – MAR 28 2016
Page 45 of 54
5. PICO Compute Module Pinmux Overview
Many signals on the PICO-IMX6UL-EMMC can be configured to support other interfaces. The table
below gives an overview of all pins that can be modified.
The default operation mode which is compatible with other PICO Compute Modules has been
highlighted.
PIN CPU BALL PADNAME MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MODE6 MODE8
E1_3 K13 GPIO1_IO00 i2c2.SCL gpt1.CAPTU
RE1 usb.OTG1_P
WR anatop.ENET
_REF_CLK1 mqs.RIGHT gpio1.IO[0] enet1.1588_
EVENT0_IN wdog3.WDO
G_B
E1_17 R8 ONOFF src.RESET_
B
E1_19 L15 GPIO1_IO01 i2c2.SDA gpt1.COMPA
RE1 usb.OTG1_O
C anatop.ENET
_REF_CLK2 mqs.LEFT gpio1.IO[1] enet1.1588_
EVENT0_OU
T wdog2.WDO
G_B
E1_21 K17 GPIO1_IO06 enet1.MDIO anatop.ENET
_REF_CLK1 usb.OTG_P
WR_WAKE csi.MCLK usdhc2.WP gpio1.IO[6] enet2.1588_
EVENT1_IN uart1.CTS_B
E1_22 E5 CSI_PIXCLK csi.PIXCLK usdhc2.WP rawnand.CE
3_B i2c1.SCL weim.OE gpio4.IO[18] enet1.MDC uart6.RX
E1_24 F2 CSI_VSYNC csi.VSYNC usdhc2.CLK sim1.PORT1
_CLK i2c2.SDA weim.RW gpio4.IO[19] enet2.MDIO uart6.RTS_B
E1_25 F3 CSI_HSYNC csi.HSYNC usdhc2.CMD sim1.PORT1
_PD i2c2.SCL weim.LBA_B gpio4.IO[20] enet2.MDC uart6.CTS_B
E1_26 E4 CSI_DATA00 csi.DATA[2] usdhc2.DAT
A0 sim1.PORT1
_RST_B ecspi2.SCLK weim.AD[0] gpio4.IO[21] wdog3.WDO
G_B uart5.TX
E1_27 F5 CSI_MCLK csi.MCLK usdhc2.CD_
B rawnand.CE
2_B i2c1.SDA weim.CS0_B gpio4.IO[17] enet1.MDIO uart6.TX
E1_28 E3 CSI_DATA01 csi.DATA[3] usdhc2.DAT
A1 sim1.PORT1
_SVEN ecspi2.SS0 weim.AD[1] gpio4.IO[22] sai1.MCLK uart5.RX
E1_30 E2 CSI_DATA02 csi.DATA[4] usdhc2.DAT
A2 sim1.PORT1
_TRXD ecspi2.MOSI weim.AD[2] gpio4.IO[23] sai1.RX_SY
NC uart5.RTS_B
E1_32 E1 CSI_DATA03 csi.DATA[5] usdhc2.DAT
A3 sim2.PORT1
_PD ecspi2.MISO weim.AD[3] gpio4.IO[24] sai1.RX_BCL
K uart5.CTS_B
E1_33 D15 ENET1_RXE
R enet1.RX_E
R uart7.RTS_B pwm8.OUT csi.DATA[23] weim.CRE gpio2.IO[7] global wdog
E1_34 K15 UART1_CTS uart1.CTS_B enet1.RX_CL
K usdhc1.WP csi.DATA[4] kpp.ROW[1] gpio1.IO[18] src.INT_BOO
T usdhc2.WP
E1_35 F14 ENET1_TXC
LK enet1.TX_CL
K uart7.CTS_B pwm7.OUT csi.DATA[22] anatop.ENET
_REF_CLK2
gpio2.IO[6] gpt1.CLK
E1_37 J14 UART1_RTS uart1.RTS_B enet1.TX_ER usdhc1.CD_
B csi.DATA[5] kpp.COL[1] gpio1.IO[19] gpt1.CAPTU
RE1 usdhc2.CD_
B
E1_41 F17 UART5_TXD uart5.TX enet2.CRS i2c2.SCL csi.DATA[14] kpp.ROW[7] gpio1.IO[30] csu.CSU_AL
ARM_AUT[0] ecspi2.MOSI
E1_42 G17 UART4_TXD uart4.TX enet2.TDAT
A[2] i2c1.SCL csi.DATA[12] kpp.ROW[6] gpio1.IO[28] csu.CSU_AL
ARM_AUT[2] ecspi2.SCLK
E1_43 G13 UART5_RXD uart5.RX enet2.COL i2c2.SDA csi.DATA[15] kpp.COL[7] gpio1.IO[31] csu.CSU_IN
T_DEB ecspi2.MISO
E1_44 G16 UART4_RXD uart4.RX enet2.TDAT
A[3] i2c1.SDA csi.DATA[13] kpp.COL[6] gpio1.IO[29] csu.CSU_AL
ARM_AUT[1] ecspi2.SS0
E1_45 K14 UART1_TXD uart1.TX enet1.RDAT
A[2] i2c3.SCL csi.DATA[2] kpp.ROW[0] gpio1.IO[16] snvs_hp_wra
pper.VIO_5_
CTL spdif.OUT
E1_46 H17 UART3_TXD uart3.TX enet2.RDAT
A[2] can2.TX csi.DATA[1] kpp.ROW[4] gpio1.IO[24] gpt1.COMPA
RE3 anatop.OTG
1_ID
E1_47 K16 UART1_RXD uart1.RX enet1.RDAT
A[3] i2c3.SDA csi.DATA[3] kpp.COL[0] gpio1.IO[17] snvs_hp_wra
pper.VIO_5 spdif.IN
E1_48 P11 SNVS_TAM
PER2 snvs_lp_wra
pper.TAMPE
R[2] gpio5.IO[2]
E1_50 D2 CSI_DATA06 csi.DATA[8] usdhc2.DAT
A6 sim2.PORT1
_SVEN ecspi1.MOSI weim.AD[6] gpio4.IO[27] sai1.RX_DA
TA usdhc1.RES
ET_B
E1_52 D3 CSI_DATA05 csi.DATA[7] usdhc2.DAT
A5 sim2.PORT1
_RST_B ecspi1.SS0 weim.AD[5] gpio4.IO[26] sai1.TX_BCL
K usdhc1.CD_
B
E1_53 J17 UART2_TXD uart2.TX enet1.TDAT
A[2] i2c4.SCL csi.DATA[6] kpp.ROW[2] gpio1.IO[20] gpt1.CAPTU
RE2 ecspi3.SS0
E1_54 D4 CSI_DATA04 csi.DATA[6] usdhc2.DAT
A4 sim2.PORT1
_CLK ecspi1.SCLK weim.AD[4] gpio4.IO[25] sai1.TX_SYN
C usdhc1.WP
E1_55 J16 UART2_RXD uart2.RX enet1.TDAT
A[3] i2c4.SDA csi.DATA[7] kpp.COL[2] gpio1.IO[21] gpt1.COMPA
RE1 ecspi3.SCLK
E1_56 D1 CSI_DATA07 csi.DATA[9] usdhc2.DAT
A7 sim2.PORT1
_TRXD ecspi1.MISO weim.AD[7] gpio4.IO[28] sai1.TX_DAT
A usdhc1.VSE
LECT
E1_57 H14 UART2_CTS uart2.CTS_B enet1.CRS sim1.PORT0
_PD csi.DATA[8] kpp.ROW[3] gpio1.IO[22] gpt1.CLK ecspi3.MOSI
E1_59 J15 UART2_RTS uart2.RTS_B enet1.COL sim2.PORT0
_PD csi.DATA[9] kpp.COL[3] gpio1.IO[23] gpt1.COMPA
RE2 ecspi3.MISO
E1_61 H16 UART3_RXD uart3.RX enet2.RDAT
A[3] can2.RX csi.DATA[0] kpp.COL[4] gpio1.IO[25] caam_wrapp
er.RNG_OS
C_OBS epit1.OUT
E1_63 G14 UART3_CTS uart3.CTS_B enet2.RX_CL
K can1.TX csi.DATA[10] kpp.ROW[5] gpio1.IO[26] ccm.WAIT epit2.OUT
E1_65 H15 UART3_RTS uart3.RTS_B enet2.TX_ER can1.RX csi.DATA[11] kpp.COL[5] gpio1.IO[27] ccm.STOP wdog1.WDO
G_B