PICO-IMX6UL-EMMC REV. A1. HARDWARE MANUAL
– VER 1.00 – MAR 28 2016
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3.7. Serial Peripheral Interface (SPI)
The PICO-IMX6UL-EMMC features an Enhanced Configurable Serial Peripheral Interface (ECSPI)
full-duplex, synchronous, four-wire serial communication block.
The following main features are supported:
Full-duplex synchronous serial interface
Master/Slave configurable
Four Chip Select (SS) signals to support multiple peripherals
Transfer continuation function allows unlimited length data transfers
32-bit wide by 64-entry FIFO for both transmit and receive data
Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
Direct Memory Access (DMA) support
Max operation frequency up to the reference clock frequency.
For additional details, please refer to the “Enhanced Configurable SPI (ECSPI)” chapter of the
“i.MX6Ultralite Application Processor Reference Manual”.
Table 15 - SPI Channel Signal Description
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O Description
E1_53
J17
UART2_TXD
ECSPI3_SS0
1V8
Serial Peripheral Interface
Chip Select 1 signal
E1_55
J16
UART2_RXD
ECSPI3_SCLK
1V8
O
Serial Peripheral Interface
clock signal
E1_57
H14
UART2_CTS
ECSPI3_MOSI
1V8
O
Serial Peripheral Interface
master output slave input
signal
E1_59
J15
UART2_RTS
ECSPI3_MISO
1V8
I
Serial Peripheral Interface
master input slave output
signal
