IPmux-24
TDM Pseudowire Access Gateway
The unit employs various pseudowire
encapsulation methods, including TDMoIP,
CESoPSN, SAToP, CESoETH (MEF 8) and
HDLCoPSN.
Proper balance between PSN throughput
and delay is achieved via configurable
packet size.
A jitter buffer compensates for packet
delay variation (jitter) of up to 180 msec
in the network.
PSEUDOWIRE QoS/CoS
Ethernet networks – outgoing pseudowire
packets are assigned a dedicated VLAN ID
according to 802.1q and marked for
priority using 802.1P bits.
IP networks – outgoing pseudowire
packets are marked for priority using
DSCP, ToS, or Diffserv bits.
MPLS networks – outgoing pseudowire
packets are assigned to a specific MPLS
tunnel and marked for priority using EXP bits.
PSEUDOWIRE TIMING
End-to-end synchronization between
circuits is maintained by deploying
advanced clock recovery mechanisms.
Clock recovery conforms to G.823 and
G.824 traffic interface using
G.8261-defined scenarios.
Advanced clock recovery conforms to
G.823 synchronization interface using
G.8261-defined scenarios and achieves
16 ppb clock accuracy.
The system clock ensures a single clock
source for all TDM links. The system clock
uses master and fallback timing sources
for clock redundancy. IPmux-24 also
provides system clock input and output via
an optional external clock port.
TDM INTERFACE
One, two or four E1 or T1 ports provide
connectivity to any standard E1 or T1
device.
The E1 and T1 interfaces feature:
•
Integral LTU/CSU for long haul
applications
•
G.703 and G.704 framing modes
•
CAS and CRC-4 bit generation (E1)
•
D4/SF and ESF framing (T1)
•
Robbed bit (T1).
Figure 1. 2G/3G Cellular Backhaul
