3.6.9 PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select
Enabled to support compliance with PCI specification version 2.1.
3.6.10 PCI # 2 Access # 1 Retry
This item allows you enabled/disabled the PCI # 2 Access # 1 Retry.
3.6.11 AGP Master 1 WS Write
This implements a single delay when writing to the PCI Bus. By default, two-wait states are used by
the system, allowing for greater stability.
3.6.12 AGP Master 1 WS Read
This implements a single delay when reading to the PCI Bus. By default, two-wait states are used by
the system, allowing for greater stability.
3.6.13 PCI IRQ Actived By ( For P2BXA-V only )
This sets the method by which the PCI bus recognizes that an IRQ service is being requested by a
device. Under all circumstances, you should retain the default configuration unless advised
otherwise by your system manufacturer. The choices are Level (default) and Edge.
3.6.14 Assign IRQ For USB
This item can be found when "OnChip USB" is enabled from Integrated Peripherals menu. When
this item is Enabled, the system automatically assigns an IRQ for the USB device connected to your
system. However, if you are not using USB devices and an ISA slot address previously occupied by
the USB device will be available for the ISA slot.
3.6.15 Assign IRQ For VGA
The Enabled option allows the BIOS to auto-route an IRQ for use by a VGA card. While most of the
VGA cards do not need the IRQ assignment, certain VGA cards may need it.
3.7 Integrated Peripherals
You can control Input and Output functions from this screen.
Figure 3-7 Integrated Peripherals
ROM PCI / ISA BIOS (XXXXXXXX)
INTEGRATED PERIPHERALS
AWARD SOFTWARE, INC.
3.7.1 OnChip IDE Channel 0/1