Tait TB9100, Руководство по обслуживанию, Страница: 81 / 132

TB9100 Reciter Service Manual Network Circuitry 81
© Tait Electronics Limited January 2006
5.8 Clock Oscillator
Both the MPC and DSP incorporate phase-locked loops to generate their
respective high frequency clocks from a relatively low reference frequency.
On the ASIF, separate reference frequencies can be used for the MPC and
DSP: the MPC reference is supplied from an on-board 13MHz oscillator,
while the DSP reference is supplied from either the 13 MHz oscillator or the
reciter 12.8 MHz clock. The reciter 12.8MHz clock is normally used, so
that the DSP is operated in frequency synchronization with other reciter
clocks.
The 13.000 MHz VCTXCO, Y200, provides a clipped sinewave output of
approximately 1Vpp, which is amplified and buffered by inverter U800 to
produce an LVTTL clock signal. This is fed to the reference clock input of
the MPC, RISC_CLK, via damping resistor R806 to minimize overshoot
and reflections, and preserve signal quality on the MPC clock input.
To ensure that clipped sinewave is amplified symmetrically, preserving the
duty cycle, the output of the VCTCXO is capacitively coupled into the
input of buffer U800. This device is then biased into the centre of its linear
region via its feedback resistor, R808.
When the reciter 12.8MHz clock is used as the DSP PLL’s reference, the
clock signal, DSP_CLK_IN, from the reciter is buffered by U801.This is
then passed to the DSP reference clock input, DSP_ CLK, via damping
resistor R806.
For other applications, where the ASIF may not be attached to a reciter, the
internal 13.000 MHz clock may be routed to the DSP reference clock. In
this case, resistor R806 is omitted and resistor R805 installed.
5.9 Power Supply
The MPC and DSP require dual supply voltages, +1.8V and +1.6V
respectively, for their core logic and +3.3V in each case for their I/O drivers.
Most of the other devices on the board use +3.3V, except for the analog
output and the general-purpose inputs, which use +6V supplies.
The maximum operating current drains are 370mA from the +3.3V supply,
180mA from the 1.8V supply, 120mA from the 1.6V supply and 12mA from
the +6V supply. To minimize heat dissipation, all supplies are generated from
the in28V supply using switching regulators.
The +3.3V and +1.8V supplies are generated by a dual-phase buck
switching converter, U900; this device incorporates two switch-mode
controllers, which are operated on opposite phases of a common clock.
This arrangement forces the input current pulses from the two switchers to
add out of phase, thus reducing the peak ripple current drawn from the
input supply. The lower ripple current injects less noise back into the input
supply, hence input filtering requirements are less onerous.