Tait TB9100, Руководство по обслуживанию, Страница: 47 / 132

TB9100 Reciter Service Manual Network Circuitry 47
© Tait Electronics Limited January 2006
or 16-bit devices with multiple read or write cycles. The transfer size is
dynamically allocated by the memory controller (see
“Memory Controllers”
on page 49 ) and is encoded on the transfer size output pins, TSIZ[0..1], as
per Table 5.5 .
When writing to memory the MPC always writes 32-bit words, even when
writing an 8-bit or 16-bit value. To prevent writes to spurious byte or half-
word locations, the write enable signals, WE[0..3], and the byte select
signals, BS[0..3], select the relevant byte(s) in a word for accesses controlled
by the GPCM (see
“General-Purpose Chip Select Machine” on page 50 )
and UPMA (see “User-Programmable Machines” on page 51 ) respectively.
The MPC architecture includes provision for a parity bit to be attached to
each byte and for these parity bits to be output/checked on each memory
cycle. Parity checking is not used in the ASIF.
MPC External
Address Bus
Note
The numbering of the address bus lines on the schematic follows
the normal industry convention, ie. the lsb is A0, rather than the
PowerPC convention with A31 being the lsb. The transition from
PowerPC numbering order to normal numbering order occurs at
the MPC pins, ie. MPC A31 is connected to address bus A0, MPC
A30 is connected to A1, and so on.
The MPC’s external address bus is 32 bits wide supporting an address space
of 4Gb. Only the lower order 27 bits are used in the ASIF application to
cover the addressing requirements of the largest memory or peripheral
device. The chip select decoding is handled internally to the MPC using a
full 32-bit address decode so that devices do not appear at multiple locations
in the memory map due to incomplete address decoding.
The lower order addresses, A0 - A13, are multiplexed when accessing the
SDRAM (see
“Address Multiplexing and Command Codes” on page 63 ).
As this multiplexing occurs at a relatively high speed, series damping resistors
are fitted to these lines to improve the signal quality. The resistors reduce the
signal rise time slightly and absorb any signals reflected back from the
memory device pins.
Table 5.5 Transfer Size Encoding
TSIZ[0..1] Port Size
0 0 32-bit word
0 1 8-bit byte
1 0 16-bit half-word
1 1 reserved