Tait TB9100, Руководство по обслуживанию, Страница: 52 / 132

52 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
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burst read cycle request
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single word write cycle request
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burst write cycle request
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periodic timer request
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exception condition request
The counter continues indexing through the RAM until it encounters a
LAST codeword, signifying the end of a pattern, or a LOOP codeword to
repeat part of a pattern. Normally, the RAM pattern controls the assertion
of TA to terminate the memory cycle and reset the control lines to their idle
state.
The signals output for a single-word read and write accesses are detailed in
“SDRAM Read and Write Cycles” on page 64 , while the burst read and
write cycles are detailed in “SDRAM Burst Cycles” on page 64 .
The periodic timer request is used for initiating refresh cycles (see
“SDRAM Refresh Cycles” on page 64 ). Each UPM incorporates a timer,
which can be programmed to initiate regular requests for running a memory
refresh cycle at the required rate.
The exception condition request is only used in the case where a memory
cycle is terminated abnormally by a TEA (see
“MPC Bus Cycles” on
page 48 ) or bus monitor time out (see “Time Bases and Watchdog” on
page 42 ). Its function is to allow the UPM to ‘clean up’ after an incomplete
memory cycle, ie. it restores all the control signals to their idle states ready
for the next memory cycle.
5.2.5 RISC Peripherals
Communications
Processor Interface
Communication between RISC and CPM takes place through an internal
8k-byte dual-port RAM or through a CPM command register.
The RISC defines buffer descriptors and parameters in the dual-port RAM
to specify the required serial communications protocols. A command
register is then used to instruct the CPM to initialize its parameters and to
start and stop communications on a particular channel.
The CPM also incorporates a DMA controller (see “CPM Serial Direct
Memory Access (SDMA)” on page 54 ) so that it can directly transfer data to
or from the RISC’s main memory space.
Fast Ethernet
Controller
Note
A full description of ethernet (more properly described as Carrier
Sense Multiple Access with Collision Detection, CSMA/CD)
operation is outside the scope of this document. For those unfa-
miliar with ethernet principles, it is recommended that a standard
text (reference 21) be consulted.