QuickStart
L-1062e_9 © SYS TEC electronic GmbH 2010
23
5.4.1
Default Mapping CANopen ChipF40
In the default mapping, the 4
th
Tx PDO and the 2
nd
Rx PDO and the 4
th
Rx PDO are invalid. This results in the following arrangement of I/Os
and PDOs:
Config
1
st
Tx PDO
2
nd
Tx PDO
3
rd
Tx PDO
1
st
Rx PDO
3
rd
Rx PDO
0
DI 0...DI 7
DI 8...DI 13
AI 0...AI 1
invalid
DO 0...DO7 duty cycle
PWM 0 ... PWM 3
1
DI 0...DI 7
AI 0...AI 3
AI 4...AI 7
DO 0...DO7 duty cycle
PWM 0 ... PWM 3
2
DI 0...DI 7
DI 8...DI 15
invalid
invalid
DO 0...DO7 duty cycle
PWM 0 ... PWM 3
3
DI 0...DI 7
invalid
invalid
DO 0...DO7
DO 8...DO15
duty cycle
PWM 0 ... PWM 3
4
DI 0...DI 7
DI 8...DI 15
AI 0...AI 3
AI 4...AI 7
invalid
duty cycle
PWM 0 ... PWM 3
5
DI 0...DI 7
DI 8...DI 15
DI 16...DI 23
invalid invalid invalid
duty
cycle
PWM 0 ... PWM 3
6
DI 0...DI 7
DI 8...DI 15
AI 0...AI 3
invalid
DO 0...DO3 duty cycle
PWM 0 ... PWM 3
Table 11:
PDO Mapping for I/O‘s F40
5.4.2
Default Mapping CANopen ChipF40 V3
In the default mapping, the 4
th
Tx PDO and the 2
nd
Rx PDO are
invalid. This results in the following arrangement of I/Os and PDOs:
I/O Config
1
st
Tx PDO
2
nd
Tx PDO
3
rd
Rx PDO
1
st
Rx PDO
0
DI 0...DI 7
DI 8...DI 13
AI 0...AI 1
invalid
DO 0...DO7
1
DI 0...DI 7
AI 0...AI 3
AI 4...AI 7
DO 0...DO7
2
DI 0...DI 7
DI 8...DI 15
invalid invalid
DO
0...DO7
3
DI 0...DI 7
invalid
invalid
DO 0...DO7
DO 8...DO15
4
DI 0...DI 7
DI 8...DI 15
AI 0...AI 3
AI 4...AI 7
invalid
5
DI 0...DI 7
DI 8...DI 15
DI 16...DI 23
invalid invalid invalid
6
DI 0...DI 7
DI 8...DI 15
AI 0...AI 3
invalid
DO 0...DO3
Table 12:
PDO Mapping for I/O‘s F40 V3
Содержание CANopen ChipF40
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