INTERFACES
Symmetricom Inc
bc635VME/bc350VXI Time and Frequency Processor (Rev. E)
3-7
Offset 0x28
MASK
Reset Value 0xXX00
Table 3-8
Bit #
INT #
Source Of Interrupt
0
0
External event input has occurred.
1
1
Periodic pulse output has occurred.
2
2
Time coincidence strobe has occurred.
3
3
The one pulse per second (1pps) output has occurred.
4
4
A data packet is available in the output
FIFO.
5-15
Reserved
An interrupt source is enabled by writing a one to the mask bit corresponding to that source. An
interrupt source is disabled by writing a zero to the mask bit corresponding to that source.
Offset 0x2A
INTSTAT
Reset Value 0xXX00
The INTSTAT register has the same basic structure as the MASK register. The TFP sets bits
zero through four of this register depending upon which interrupt source generated the interrupt.
The INTSTAT register bits are set regardless of the state of the mask bits. This feature allows
the host to poll for the occurrence of the interrupt sources. INTSTAT bits are cleared by writing
to the INTSTAT register with the corresponding bit(s) set.
* * * WARNING * * *
It is the transition of an INTSTAT bit from a zero to a one that causes an interrupt to be
generated (assuming that the corresponding MASK bit was set). If the bit in the INTSTAT
register is not cleared by the host it is not possible to generate a second interrupt. It is good
programming practice to clear the INTSTAT register immediately after interrupts have been
enabled.
Offset 0x2C
VECTOR
Reset Value 0xXX00
The VECTOR
register holds the eight bit Status/ID byte that the TFP will return during interrupt
acknowledge cycles for VMEbus applications.
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