SWIR Acuros CQD Series, Руководство пользователя

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User Manual
Acuros
®
CQD
®
Camera
38 | P a g e
7.10 Master Clock
The Acuros CQD Camera Master clock has two settings, High
and Low and governs the sensor readout IC frequency.
Low master clock can be used with the Mono14 pixel format
and provides guaranteed 14bit precision on the camera’s output imagery.
High master clock speed doubles the maximum allowable frame rate for a given set of parameters,
but the readout IC settling time reduces guaranteed accuracy to 10bits. Master clock speed
combines with windowing and pixel format settings to determine the maximum possible frame
rate.
Refer to Section 7.3 for more specifics on how windowing and clock speed interact.
7.11 Gain
The Gain setting adjusts the integration capacitor in the pixel input
amplifier. Higher gain modes increase the signal to noise ratio
when the noise is dominated by the camera electronics. The Mid-
and High-Gain modes are most useful at shorter integration times,
usually below 30ms or so, and lower light levels. At longer integration times, the sensor’s
photodiode dark current can dominate and will override noise improvements seen in higher gain
modes.
The table below describes the designed full well capacitance (FWC) of the pixel input amp for each
gain mode.
Gain
mode
FWC
[e-]
High 26,000
Mid 110,000
Low 550,000
Table 10: Full Well Capacitance of Each Gain Mode
7.12 Load Factory Defaults and Save Settings
The Acuros CQD Camera parameters can be changed to achieve the desired image output. Save
Settings will record all the current camera parameters into nonvolatile memory which will
Figure 29: Master Clock
Pull-Down Menu
Figure 30: Gain Mode
Pull-Down Menu