SWIR Acuros CQD Series, Руководство пользователя, Страница: 111 / 121

User Manual
Acuros
®
CQD
®
Camera
111 | P a g e
10.5 Software Command Protocol Appendices
10.5.1 Appendix_A: FPGA Serial Bus and Register Map
Serial Bus
The diagram below shows the serial bus timing for the FPGA interface. It is a read/write bus with
7 bits of addressing and 16 bits of data (e.g. up to 127, 16-bit registers). The first bit in the
sequence defines either a read or write cycle.
FPGA Register Write
SER_CLK
SELECT
SER_DAT_IN
SER_DAT_OUT
A2 A3 A4 A5 A6 D0 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D3
FPGA Register Read
SER_CLK
SELECT
D0 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D3
SER_DAT_IN
A3 A4 A5 A6
RnW A0 A1
RnW A0 A1 A2
The FPGA is a slave on the serial bus. The master resides within the PIC uC. An FPGA register
write is accomplished by sending 3 bytes. An FPGA register read is accomplished by sending one
byte to the FPGA then reading two bytes. The PIC clock mode 2 (CKP=0, CKE=1) is used.