Supero X10SRL-F, Руководство пользователя

Страница: 48 / 129

2-22
X10SRL-F User’s Manual
BIOS LICENSE
IPMI CODE
MAC CODE
BAR CODE
DESIGNED IN USA
1.01 Rev:
X10SRL-F
1
+
LAN
CTRL
LAN
CTRL
BMC
JP3
JTPM1
JF1
JD1
T-SGPIO1
T-SGPIO2
T-SGPIO3
JOH1 JL1
JPME2
JWD1
JPG1 JPB1
JI2C2 JI2C1
JBR1
JPL2
JPL1
JVR1
JSD1
JSD2
JIPMB1
JPWR1
UID LED - LE1
LE2
LEDM1
JBT1
BT1
FAN4
FAN1 FAN2
FAN3
FANA
FAN5
J24
JPI2C1
JSTBY1
S-SATA3
I_SA
TA4
I-SATA0 I-SATA1 I-SATA2 I-SATA3
S-SA
TA0
S-SA
TA1
S-SATA2
I-SATA5
SP1
CPU
CPU SLOT5 PCI-E 3.0 X8 CPU SLOT4 PCI-E 3.0 X8(IN X16)
USB0/1
DIMMC2
USB8/9
USB6/7
USB2/3(3.0)
LAN1
DIMMA2 DIMMA1
USB10(3.0)
LAN2
USB4/5
CPU SLOT2 PCI-E 3.0 X4(IN X8) PCH SLOT1 PCI-E 2.0 X4(IN X8)
COM2
COM1
DIMMB2 DIMMB1 DIMMD2 DIMMD1
IPMI_LAN
UID - SW
5V STBY
USB11(3.0)
IPMI
VGA
CPU SLOT7 PCI-E 3.0 X8
DIMMC1
CPU SLOT3 PCI-E 3.0 X4(IN X8)
CPU SLOT6 PCI-E 3.0 X8(IN X16)
Intel PCH
1
1
Power Button
OH/Fan Fail LED
1
NIC1 LED
Reset Button
2
HDD LED
Power LED
Reset
PWR
P3V3
P3V3_STB
P3V3_STB
P5V_STB
Ground
Ground
19 20
P3V3
X
Ground
NMI
X
P3V3_STB
PWR Fail LED
NIC2 LED
Front Control Panel Pin Definitions
A. NMI
B. PWR LED
A
B
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin definitions.
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin definitions.
NMI Button
Pin Definitions (JF1)
Pin# Definition
19 Control
20 Ground
Power LED
Pin Definitions (JF1)
Pin# Definition
15 3.3V
16 PWR LED