Supero X10DRG-Q, Руководство пользователя

Страница: 54 / 123

2-30
X10DRG-Q Motherboard User’s Manual
S-SGPI
O
I-SGPIO
2
BAR CODE
X10DRG-Q
Rev.1.01
MAC CODE
FA
N3
FA
N4
FA
N6/CPU
2
FA
N5/CPU
1
FA
N1
FA
N2
FA
NA
FANB
FANC FAND
JBT1
LED1
SP1
J2
3
JVR1
JP
AC
1
JVRM
2
JVRM
1
JWD1
JPME
2
JPG1
JPB1
JPL1
JI2C
2
JI2C
1
JTPM
1
JSD1
JSD2
JHD_AC
1
JSPDIF_IN1
JL
1
JITP
1
JPI2C1
JTBT
1
BIOS
LICENSE
S-SA
TA
0
S-SA
TA
1
I-SA
TA
4
I-SA
TA
5
S-SA
TA
3
S-SA
TA
2
I-SA
TA
1
I-SA
TA
2
I-S
AT
A3
I-SA
TA
0
IPMI CODE
JIPMB1
AUDIO_FP
COM1
JBAT1
JPWR
4
JPWR
2
FA
N-I1
COM2
SUPERDO
M
USB 6 (3.0)
P1-DIMMC
1
P1-DIMMC
2
AL
WA
YS POPULA
TE DIMMx1 FIRST
CPU1
P1-DIMMD
2
P2-DIMME
1
P2-DIMMF
1
P2-DIMME
2
P2-DIMMF
2
LAN2
CPU2
P1-DIMMB
2
P1-DIMMB
1
LAN1
P1-DIMMA
1
P1-DIMMA
2
AL
WA
YS POPULA
TE DIMMx1 FIRST
IPMI_LAN
USB 4/5(3.0) USB 0/1
P2-DIMMG
1
P2-DIMMH
1
P2-DIMMG
2
AL
WA
YS POPULA
TE DIMMx1 FIRST
P2-DIMMH
2
VGA
CPU2 SLOT
11
PCI-E 3.0 X8
CPU1 SLOT10 PCI-E 3.0 X8(IN X16)
PCH SLOT9 PCI-E 2.0 X4(IN X8
)
CPU2 SLOT8 PCI-E 3.0 X1
6
CPU2 SLOT6 PCI-E 3.0 X1
6
CPU1 SLOT4 PCI-E 3.0 X1
6
USB 7/8(3.0)
CPU1 SLOT2 PCI-E 3.0 X1
6
USB 2/3
JPWR
3
JPWR
1
JF
1
I-SGPIO
1
P1-DIMMD
1
CLOSE 1st
OPEN 1st
CLOSE 1st
OPEN 1st
LAN
CTRL
BMC
BIOS
PCH
LEDM1
JSTBY1
LED2
SMBus for IPMI
A 4-pin external BMC System Man-
agement Bus (I
2
C) header for IPMI
2.0 with support of NVMe (Non-
Volatile Memory Express) and SGPIO
(Serial-Link General Purpose I/O) is
located at JIPMB1. Connect an ap-
propriate cable here to use the IPMB
I
2
C connection with NVMe and SGPIO
support on your system.
IPMB Header
Pin Definitions
Pin# Definition
1 Data
2 Ground
3 Clock
4 No Connection
A. Chassis Intrusion
B. JIPMB1
A
Chassis Intrusion
A Chassis Intrusion header is located
at JL1 on the motherboard. Attach an
appropriate cable from the chassis to
inform you of a chassis intrusion when
the chassis is opened.
Chassis Intrusion
Pin Definitions
Pin# Definition
1 Intrusion Input
2 Ground
B