Supero Supero X9SRL, Руководство пользователя

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2-26
X9SRL Motherboard Series User’s Manual
1
JD1 7
JIPMB1
C
A
4
5
8
1
JPW2
I-S
AT
A5
I-SATA4 I-SATA3
I-S
AT
A2
2
UID_SW
1
DIMM_C1 DIMM_C2 DIMM_D1
DIMM_A1
DIMM_B1 DIMM_A2 DIMM_B2
DIMM_D2
I-SATA1
I-SATA0
I-SAS3
I-SAS2
I-SAS1
I-SAS0
7
JVGA
2
1
JF1
19
20
JKBMS1
C A
UID_LED
JLAN_USB12
X_BT1
+
5
JPI2C
1
1
JBT1
1
JPW1
13
JUSB2
3-SGPIO1
2
8
T-SGPIO2 T-SGPIO1
JOH1
1
JL1
1
JI2C
2
1
JI2C
1
A
DP3
C A
JPBIOS
1
JP
ME1
1
JIBTN1
3
1
3
JWD1
JVR2
3
1
JPL2
1
JPL
1
1
3
JVR1 1
3
1
JPUSB1
3
3
JPG1
1
JPB1
1
FANA
FAN5
1 4
FAN3
FA
N4
1
FAN2
4
1
FAN1
4
MH11
MH1
MH5
MH9
MH8
MH2
MH10
JCOM1
PCIE
6
PCIE
5
PCIE
4
PCIE
3
PCIE
7
2
JTPM1
PCIE
1
PCIE
2
JPK1
1 3
JSD1 JSTB
Y1
1 3
JLAN1 JLAN2
RE
V:
1.00
Tested to
Co
mply
Wi
th FC
C Standards
FOR HOME OR OFFICE US
E
DESIGNED IN USA
BAR CODE
JC
OM2
1
5
6
9
1
7
2 JUSB4
5
1
7
2
JUSB67
1
7
JUSB89
P1-DIMM2
D
P1-DIMM2
C
P1-DIMM1
C
P1-DIMM1
D
P1-DIMM2B
P1-DIMM2A
CPU1
SL
OT
7 PCI-E 3.0X8 (INX8)
SL
OT
6 PCI-E 3.0X8 (INX16)
SL
OT
5 PCI-E 3.0X8 (INX8)
SL
OT
4 PCI-E 3.0X8 (INX16)
SL
OT
3 PCI-E 3.0X4 (INX8)
SL
OT
2 PCI-E 3.0X4 (INX8)
SL
OT
1 PCI-E 2.0X4 (INX8)
X9SR
L
JPK1
JP
ME
1
JBT1 C
OMS CLEAR
JPBIOS1
JL1 CHASSIS INTRUSION
JSD1:SATA DOM POWER
JPI2C1:PWRI2
C
JT
PM
1:TP
M/PORT80
ON:ME RE
CO
VERO
S
OF
F:
NORMAL
CO
M2
Pin1:RAID_KEY_PCH
Pin3:PCH_DYN_SKU
Pin2:Ground
JPB1
1-2 Enable
2-3 Disable
1-2:NORMAL
2-3:RECOVER BIOS
1-2 Enable
2-3 Disable
JPG1: VGA
OFF:DISABLE
JI2C1/JI2C2
ON: ENABLE
UID
RST ON PW
R
LAN2
PW
R FF OH
FA
IL
HD
D LE
D
PW
R
X
NIC
1 2
NIC NM
I
LAN1
2-3:NMI
1-2:RST
2-3 Disable
1-2 Enable
JWD1:Watch Dog
JPL1/2: LAN
PWR LED
SPEAKER
1-3:
4-7:
JD1:
VGA
CO
M1
IPMI_LAN
USB0/1
2-3 ENable
P1-DIMM1B
KB/MOUSE
1-2 Disable
JPUSB1:USB Wake Up
P1-DIMM1A
C
Serial_Link-SGPIO
Pin Definitions
Pin# Definition Pin Definition
1 NC 2 NC
3 Ground 4 DATA Out
5 Load 6 Ground
7 Clock 8 NC
A. T-SGPIO1
B. T-SGPIO2
T-SGPIO & SCU-SGPIO Headers
Two T-SGPIO (Serial-Link General Purpose
Input/Output) headers are supported on the
motherboard. Additionally, one SCU-SGPIO
port (for SCU) is also located next to USB 8/9.
These headers are used to communicate with
the enclosure management chip in the system.
See the table on the right for pin definitions.
Refer to the board layout below for the loca-
tions of the headers.
Trusted Platform Module Header
Pin Definitions
Pin # Definition Pin # Definition
1 LCLK 2 GND
3 LFRAME 4 No Pin
5 LRESET 6 VCC5
7 LAD3 8 LAD2
9 VCC3 10 LAD1
11 LAD0 12 GND
13 RSV0 14 RSV1
15 SB3V 16 SERIRQ
17 GND 18 CLKRUN
19 LPCPD 20 RSV2
TPM Header (JTPM1)
This header is used to connect a Trusted Plat -
form Module (TPM), which is available from a
third-party vendor. A TPM is a security device
that supports encryption and authentication in
hard drives. It enables the motherboard to deny
access if the TPM associated with the hard
drive is not installed in the system. See the
table on the right for pin definitions.
D
C. SCU-SGPIO1
D. TPM Header
A
B