Supero PDSMA+, Руководство пользователя

Страница: 15 / 119

Chapter 1: Introduction
1-9
1-2 Chipset Overview
The Intel 3000/3010 chipset, designed for use with the Pentium 4 Processor in the
LGA 775 Land Grid Array Package, is comprised of two primary components: the
Memory Controller Hub (MCH) and the I/O Controller Hub (ICH7R). In addition,
Intel's PCI-X (PXH-V) is used for added functionality. The PDSMA+/PDSMA-E+
provides the performance and feature-set required for the high-end UP Server
market.
Memory Controller Hub (MCH)
The function of the MCH is to manage the data flow between four interfaces: CPU
interface, DDR2 System Memory Interface, PCI Express Interface, and Direct Media
Interface (DMI). The MCH is optimized for the Pentium 4 processor in the LGA775
Land Grid Array Package. It supports one or two channels of DDR2 SDRAM.
The I/O Controller (ICH7R) provides the data buffering and interface arbitration re-
quired for the system to operate efficiently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH7R. The ICH7R supports
up to six PCI-Express slots, four Serial ATA ports, six USB 2.0 ports and two IDE
devices. In addition, the ICH7R offers the Intel Matrix Storage Technology which
provides various RAID options for data protection and rapid data access. It also
supports the next generation of client management through the use of PROActive
technology in conjunction with Intel's next generation Gigabit Ethernet controller.
Intel ICH7R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
*Advanced Configuration and Power Interface, Version 2.0 (ACPI)
*Intel I/O External Design Specification (EDS)
*Intel's 3000/3010 Memory Controller Hub (MCH) External Design Specification
(EDS)
*Intel I/O Controller Hub 7 (ICH7R) Thermal Design Guideline
*Intel 82573 Platform LAN Connect (PLC) PCI Design
*Low Pin Count (LPC) Interface