Supermicro X7DB3, Руководство пользователя

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Chapter 1: Introduction
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1-2 Chipset Overview
Built upon the functionality and the capability of the 5000P chipset, the X7DB3
motherboard provides the performance and feature set required for dual pro-
cessor-based servers with con
fi guration options optimized for communications,
presentation, storage, computation and database applications. The 5000P chipset
supports single or dual 64-bit quad core/dual core processor(s) with front side bus
speeds of up to 1.333 GHz/1.066 GHz/677 MHz. The chipset consists of the 5000P
Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O
subsystem (PXH).
The 5000P MCH chipset is designed for symmetric multiprocessing across two inde-
pendent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz
data bus that transfers data at 10.7 GB/sec. (for a total bandwidth of 21.3GB/sec.).
The MCH chipset connects up to eight Fully Buffered DIMM modules, providing
a total memory bandwidth of 32 GB/s for DDR2 533/667. The MCH chipset also
provides one x8 PCI-Express and one x4 ESI interfaces to the ESB2. In addition,
the 5000P chipset offers a wide range of RAS features, including memory interface
ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirror-
ing and memory sparing.
The Xeon Quad core/dual core Processor Features
Designed to be used with conjunction of the 5000P chipset, the Xeon quad core/dual
core Processor provides a feature set as follows:
The Xeon Quad core/dual core Processors
L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
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L2 Cache Size: 4MB/2MB (per core)
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*Data Bus Transfer Rate: 8.5 GB/s
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Package: FC-LGA6/FC-LGA4, 771 Lands
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