Supermicro X12SPG-NF, Руководство пользователя

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Chapter 4: BIOS
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Data Scrambling for DDR4
Use this feature to enable or disable data scrambling for DDR4 memory. The options
are Disable and
Enable .
2x Refresh Enable
Use this feature to enable 2x memory refresh support to enhance memory performance.
The options are
Auto , Disable, and Enable.

Memory Topology
This feature displays the information of memory modules detected by the BIOS.

Memory RAS Configuration Setup
Enabled Pcode WA for SAI PG
Use this feature to enable Pcode Work Around for SAI Policy group for A Step. The
options are
Disabled and Enabled.
Correctable Error Threshold
Use this feature to specify the threshold value for correctable memory-error logging,
which sets a limit on the maximum number of events that can be logged in the memory
error log at a given time. The default setting is
512 .
Partial Cache Line Sparing PCLS
Use this feature to enable or disable Partial Cache Line Sparing (PCLS). The options
are Disabled and
Enabled .
ADDDC Sparing
Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede-
termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are Disabled
and
Enabled
.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub reads and writes back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub is scrubbed every day. The op-
tions are Disabled, Enabled, and
Enable at End of POST .