Super X12SCZ-TLN4F/QF/F User's Manual
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Max CPU Speed
•
Min CPU Speed
•
CPU Speed
•
Processor Cores
•
Hyper Threading Technology
•
VMX
•
SMX/TXT
•
64-bit
•
EIST Technology
•
CPU C3 state
•
CPU C6 state
•
CPU C7 state
•
CPU C8 state
•
CPU C9 state
•
CPU C10 state
•
L1 Data Cache
•
L1 Instruction Cache
•
L2 Cache
•
L3 Cache
•
L4 Cache
C6DRAM (Available when supported by the CPU)
This feature enables moving DRAM contents to PRM memory when the CPU is in a C6 state.
The options are Disabled and
Enabled
.
Hardware Prefetcher
If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disable
and
Enable
.
