60
Super X12DPG-AR User's Manual
BIOS LICENSE
BMC CODE
BAR CODE
X12DPG-AR
REV:1.01
DESIGNED IN USA
JAIOM1
J32
JPW1
JRU1
JFP1
JHDD_PWR1
JHDD_PWR2
JUSB1
BMC_LAN1
JBT1
BT1
JNCSI1
JPWR_RISER1
JTPM1
JIPMB1
JC
OM1
JVGA1
JUIDB1
JM2
JRK1
JL1
JSTBY1
JPW3
JPW4
JPW5
JPW6
JPW2
JS2
JS1
LE6
LEDM1
LE3
JGP
U1
JGP
U4
JGP
U3
JGPU
5
JGPU
6
FAN
B
FAN
A
FAN
1
FAN
2
FAN3
FAN
4
FANF
FAN
E
FAN
C
JN
VME1
JN
VME2
JGPU2B
JRIO1
JGP
U2A
Ba�ery
CPU2 P
CI-E 4.0 X8
CPU1 P
CI-E 4.0 X16
CPU1 P
CI-E 4.0 X16
CPU2 P
CI-E 4.0 X8
CPU1 P
CI-E 3.0 X8
CPU1 P
CI-E 4.0 X16
CPU1 P
CI-E 4.0 X8
AIOM CPU1 PCI-E 4.0 X8
(3.0)
USB2/3
I-S
ATA0~3
I-S
ATA4~7
P1-DIMMB1
P1-DIMMC1
P1-DIMMD1
P1-DIMMA1
P2-DIMMF1 P2-DIMME1 P2-DIMMH1 P2-DIMMG1
TPM/POR
T80
VR
OC K
EY
(3.0)
USB0/1
CPU1
CPU2
P2-DIMMC1
P1-DIMMH1
P1-DIMMG1
P2-DIMMD1 P2-DIMMA1 P2-DIMMB1
P1-DIMME1 P1-DIMMF1
CPU2 P
CI-E 4.0 X8
CPU2 P
CIE
-E 4.0 X16
CPU2 PCI-E 4.0 X8
CPU2 P
CIE
-E 4.0 X16
VG
A
COM1
BMC External I
2
C Header
A System Management Bus header for BMC (Baseboard Management Controller) is located
at JIPMB1. Connect the appropriate cable here to use the IPMB I
2
C connection on your
system. Refer to the table below for pin definitions.
1
1. JIPMB1
External I
2
C Header
Pin Definitions
Pin#
Definition
1
Data
2
Ground
3
Clock
4
P3V3_STBY