Supermicro SUPERSERVER 1028R-TDW, Руководство пользователя

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Chapter 7: BIOS
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ERVER 1028R-TDW User's Manual
codes to overwhelm the processor to damage the system during an attack. This
feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX,"
and "Lock Chipset" for Virtualization media support. The options are
Enable and
Disable. (Refer to Intel and Microsoft websites for more information.)
PPIN Control
Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in
the system. The options are
Unlock/Enable and Unlock/Disable.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enable, the hardware prefetcher will prefetch streams of data and instruc-
tions from the main memory to the L2 cache to improve CPU performance. The
options are Disable and
Enable .
Adjacent Cache Prefetch (Available when supported by the CPU)
Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.
Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options
are Disable and
Enable .
Note : Please reboot the system for changes on this setting to take effect.
Please refer to Intel’s website for detailed information.
DCU (Data Cache Unit) Streamer Prefetcher (Available when supported by
the CPU)
If set to Enable, the DCU Streamer Prefetcher will prefetch data streams from the
cache memory to the DCU (Data Cache Unit) to speed up data accessing and
processing to enhance CPU performance. The options are Disable and
Enable .
DCU IP Prefetcher
If set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will prefetch IP
addresses to improve network connectivity and system performance. The options
are
Enable and Disable.
X2APIC (Advanced Programmable Interrupt Controller)
Based on Intel's Hyper-Threading architecture, each logical processor (thread) is
assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-
able, the APIC ID will be expanded from 8 bits (X2) to 16 bits to provide 512 APIDs
to each thread to enhance CPU performance. The options are
Disable and Enable.
AES-NI
Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc-
tions (NI) to ensure data security. The options are Enable and
Disable .

CPU Configuration
This submenu displays the following CPU information as detected by the BIOS. It
also allows the user to configure CPU settings.
•
Processor Socket
•
Processor ID
•
Processor Frequency
•
Processor Max Ratio
•
Processor Min Ratio
•
Microcode Revision
•
L1 Cache RAM
•
L2 Cache RAM
•
L3 Cache RAM
•
CPU 1 Version
•
CPU 2 Version
Clock Spread Spectrum
Select Enable to allow the BIOS to monitor and attempt to reduce the level of
Electromagnetic Interference caused by the components whenever needed. The
options are
Disable and Enable.
Hyper-Threading (All)
Select Enable to support Intel's Hyper-threading Technology to enhance CPU per-
formance. The options are
Enable and Disable.
Cores Enabled
This feature allows the user to set the number of CPU cores to enable. Enter "0"
to enable all cores. The default setting is
0 .
Execute-Disable Bit (Available if supported by the OS & the CPU)
Select Enable for Execute Disable Bit Technology support, which will allow the
processor to designate areas in the system memory where an application code can
execute and where it cannot, thus preventing a worm or a virus from flooding illegal