16
Chapter 1: Introduction
System Block Diagram
The block diagram below shows the connections and relationships between the subsystems
and major components of the overall system.
Figure 1-6. System Block Diagram
5
4
3
2
D
C
B
A
Up to 3200MT/s
PHY
UPLINK DMI3
RTL8211F
Gen Z
SlimSASx8
SlimSASx8
PCIe 4.0 X4 X4 X4 X4
Support 4 x U.2 NVMe
USB2.0
PCH
C621A
CPLD
FLASH
Support 2 x U.2 NVMe
PCIe 4.0 X4 X4
PCIe 4.0 X4 X4 or X8
PCIe 4.0 X16
Note: DIMM Layout Implementation
Up to 3200MT/s
PCIe 4.0 X16
I-SATA x8
P1
#5
#2
DD
R
4 DIMM
SYS
SPI
ICX
SKT-P+
DD
R
4 DIMM
DD
R
4 DIMM
ICX
SKT-P+
RGRMII
2
#
7
#
CPLD
(PFR)
#0,1,2,3
P3
SlimSASx4
#8
DD
R
4 DIMM
DD
R
4 DIMM
TMP432
AIOM
BMC
P2
DD
R
4 DIMM
CPU 2
RMII/NCSI
DD
R
4 DIMM
#4
DD
R
4 DIMM
CPU 1
PCI-E X1
DD
R
4 DIMM
DD
R
4 DIMM
BMC
FLASH 0
P1
USB 2.0
#5
DD
R
4 DIMM
UPI
COM1
Connector
(Internal)
P3
ESPI
#8
Temp Sensor
DDR4
NCSI
master
#10,11
USB 3.0
SPI
#5
10.4GT/s
or 11.2GT/s
P0
S-SATA x2
7-Pin
DD
R
4 DIMM
DD
R
4 DIMM
P2
6.0 Gb/S
#3
DD
R
4 DIMM
DD
R
4 DIMM
P0
AST2600
1
#
4
#
P3 P1 P0 P2 DMI3
DD
R
4 DIMM
U
SB
7
#
6
#
PCIe Slot
RJ45
6.0 Gb/S
#3
P0 P1 P2 P3 DMI3
#1
#7, 8
USB 2.0
SPI
VGA CONN
#6
8
#
4
#
#3
#7
#7
CPU 2
#5
#2
#8
#6
#1
#5
#1
CPU 1
#4
#6
PCIe 3.0 X4
#9
VR
VR
Dual Boot
FLASH
#1,2
#12, 13
BIOS
FLASH0
TPM HEADER
Debug Card
#2
#3
