13
Chapter 1: Introduction
Figure 1-4. Motherboard Layout
1.5 Motherboard Layout
Below is a layout of the H12SSW-NT with jumper, connector and LED locations shown. See
the table on the following page for descriptions. For detailed descriptions, pinout information
and jumper settings, refer to Chapter 4.
Notes:
•
" " indicates the location of Pin 1.
•
Jumpers/components/LED indicators not indicated are used for internal testing only.
J19
H12SSW-iN
MEGER
AC LICENSE
MAC CODE
IP
MI C
ODE
BAR CODE
BT1
+
MH15
JSXB2
+
JTP
M1
1
2
JUSBA1
4
1
5
9
JF1
1
2
JSD2
1
3
JSD1
1
3
1
JNCSI1
JUSBRJ45
LED6
A
C
LED1
LED11
LED12
LED10
LED13
JDB2 JDB1
JWD1
JPL1
JPG1
JU
AR
T2
JPB1
1
3
JU
AR
T3
JHD
T1
JFPGA_SW1
2
7
8
JVRM1
JSLIM3
B1
JSLIM2
JSLIM1
1 2 3
FAN6
FAN5
FAN4
FAN3
FAN2
FAN1
1
JOH1
JL1
JPWR2
4
1
2
3
JIP
MB1
JSXB1B
JPWR1
JB
T1
MH4
MH17
JSXB1A
JSXB1C
MH8
MH6
MH9
SXB1C
SXB1B: PCI-E 4.0 X16 + X16
SXB1A
SXB2: PCI-E 4.0 X16
1-2:RST
2-3:NMI
JWD1:W
AT
CH DOG
CMOS CLEAR
1-2:NORM
AL
2-3:BIOS REC
OVER
Y
JDB1
:OH-LED
SA
TA16
SA
TA17
SA
TA8-15
SA
TA0-7
NVME4/5
NVME2/3
NVME0/1
USB5/6(3.0)
SUPERDOM
+
CPU_POR
T2A
CPU_POR
T1A
CPU_POR
T1C
UID-SW
UID
-LED
BATTERY
DIMMB1
DIMMC1
DIMMD1
VGA
DIMM
A1
DIMMG1
DIMME1 DIMMF1
DIMMH1
JPB1:BMC
1-2:ENABLE
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPG1:VGA
BMC
M.2-HC2
CPU PCI_E 4.0 X2
M.2-HC1
CPU PCI-E 4.0 X4/X2
M.2-HC2 ACT
M.2-HC1 ACT
M.2-HC1 ERR
BUZZER
M.2-HC2 ERR
USB4(3.0)
JPL1/LAN
2-3:DISABLE 1-2:ENABLE
JCPLD1
1
5
LAN2
LAN1
JCOM1
COM1
(3.0)
USB2/3
(3.0)
USB0/1
IPMI_LAN
CPU
LED 6
SXB1A
SXB2
SXB1B
SXB1C
USB 5/6 (3.0)
JWD1
NVME 0/1
NVME 2/3
FAN 3
FAN 2
FAN 1
JPWR1
JPWR2
PWRI2C
JF1
TPM/PORT80
JPL1
COM2
JIPMB1
COM1
USB 0/1
USB 2/3
LAN 1
LAN 2
VGA
UID SW
LED 1
M.2-C2
M.2-C1
LED 12
BATTERY
JBT1
USB 4 (3.0)
IPMI LAN
FAN 6
FAN 5
FAN 4
JL1
NVME 4/5
SATA1
SATA0
JSD1
JSD2
SATA 8-15
JOH1
BUZZER
SATA 0-7
LED 11
JCPLD1