Sun Microsystems Netra T4 AC100, Руководство по обслуживанию и системе

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10-6 Netra T4 AC100/DC100 Service and System Reference Manual • August 2001
Thermal management relies on high air flow and a large heat sink radiation area to
maintain uniform temperature control for the CPU module(s). The temperature of
the CPU module(s) is monitored to avoid any destructive effect in case of fan failure.
The CPU die contains a temperature sensing diode that is connected to a
temperature controller located off the die. This temperature controller performs the
analog-to-digital temperature conversion and is interfaced through the I2C serial
bus.
10.2.2 Main Memory
The memory subsystem comprises to memory groups and four logical banks. The
memory groups are divided into even and odd slots. A configuration is valid only if
at least the odd or even slots are filled with four DIMMs of the same density.
FIGURE 10-4
Memory Subsystem
10.2.2.1 Organization
As shown on
FIGURE 10-1,
direct access to the system main memory is controlled only
by one of the two CPU modules in a multiprocessor environment. Memory is
accessed from UltraSPARC Processor 0 through the Sun CrossBar Interconnect bus.
The main memory data bus is 576 bits wide, which corresponds to an external cache
block of 64 bytes. The systems main memory delivers an entire block of information
on external cache in a single memory bus cycle. This delivery method provides up to
2.4 Gbps of sustainable bandwidth.
Even Slots
Odd Slots
0 0 0 0
1 1 1 1
Address Bus
Buffers
Control Bus
UltraSPARC III
CPU 0
Data - 576 bits
Safari Data Bus
Address Bus