Sun Microsystems Netra T4 AC100, Руководство по обслуживанию и системе

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10-2 Netra T4 AC100/DC100 Service and System Reference Manual • August 2001
10.2 System Overview
The Netra T4 AC100 is available as a single or dual UltraSPARC-III processor
controlled server system. The Netra T4 uses shared-memory multiprocessor
architecture with both processors installed on a single motherboard (See
FIGURE 10-1
.
Each UltraSPARC-III processor has a memory controller installed within the
processor. When two UltraSPARC-III modules are installed on a Netra T4 system,
only the memory controller installed in CPU slot 0 is enabled.
The Netra T4 I/O subsystem is designed around a system bus controller (SBC) ASIC,
which is a bridge between the Sun CrossBar Interconnect address bus and the
33 MHz and 66 MHz PCI buses.
The two PCI buses interface with the FC-AL controller and any other boards that are
installed in the PCI slots. A 33 MHz PCI bus (PCI-B) supports SCSI controllers that
interface with the internal DVD-ROM, or DAT drives. A 66 MHz PCI bus (PCI-A or
EPCI for extended PCI bus) supports the Fibre Channel-Arbitrated Loop (FC-AL)
controller that interfaces with the hard disk drives.
The 33 MHz PCI-B I/O buses support the Peripheral Component I/O-2 (PCIO-2)
ASIC. This ASIC is an interface between the 33 MHz PCI bus, external universal
serial buses (USB), the 10/100 Mbit Ethernet ports, the boot PROM, and the EBus.
Note –
EBus is a slow byte-wide bus for low-speed devices such as the serial port
controller, the SuperI/O controller (used primarily as a parallel port interface), and
the boot PROM.
A BootBus controller (BBC) ASIC is connected to both UltraSPARC-III modules
through a shared BootBus. The BBC ASIC bridges the BootBus to the EBus, to which
slow I/O devices and the boot PROM are attached. The BBC ASIC incorporates an
inter-integrated circuit (I2C) bus interface and a JTAG master controller. The I2C
controller is used to identify the processor modules, the DIMMs and for
environmental control. The JTAG master controller is used for boundary testing on
the system board, ASIC, and processor testing.