STP1612PW05
Setting the PWM gray scale counter
Doc ID 15819 Rev 4
19/35
9.2
Synchronization for PWM counting
The data synchronization between the incoming data flow and the output channels is
managed through the bit A within the configuration register.
If the bit A is set to “0” the device performs itself the data synchronization: when all the new
data are loaded with a “global latch”, the device wait until all the PWM counter completes
the counting cycle before updating them with the new data, at the next CLK rising edge.
Conversely, if bit A is set to “1” (default), the data synchronization is not performed by the
device and is managed by the microcontroller, which has to take care of the data and
signals. If this is not done, there might be artefacts on the output image.
Figure 9.
Synchronization for PWM counting
Figure 10.
Without synchronization for PWM counting
CLK
PWCLK
CLK
PWCLK
Содержание STP1612PW05
Страница 3: ...STP1612PW05 Contents Doc ID 15819 Rev 4 3 35 16 Package mechanical data 25 17 Revision history 34...
Страница 28: ...Package mechanical data STP1612PW05 28 35 Doc ID 15819 Rev 4 Figure 17 SO 24 package dimensions...
Страница 32: ...Package mechanical data STP1612PW05 32 35 Doc ID 15819 Rev 4 Figure 20 QFN24 4x4 mechanical drawing...
