STMicroelectronics STM3210E-EVAL, Руководство пользователя

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UM0488 Hardware layout and configuration
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2.20 NOR Flash
128 Mbit NOR Flash is connected to bank1 NOR/PSRAM2 of the FSMC interface. The 16-
bit operation mode is selected by a pull-up resistor connected to the BYTE pin of the NOR
Flash. Write protection can be enabled or disabled by jumper JP5.
Three different NOR 128-Mbit references can be present on the evaluation board depending
on component availability.
These three references are not identical in terms of ID code, speed, timing or block
protection. The demonstration firmware and the software library delivered with the board
support these three NOR Flash references. However, during the development of your
application software, you must verify which NOR reference is implemented on your board
(component referenced as U2 on silkscreen and schematic), and take its characteristics into
account.
Table 14. NOR Flash related jumpers
Jumper Description
JP5
Write protection is enabled when JP5 is fitted.
Write protection is disabled when JP5 is not fitted (default setting).
Table 15. NOR Flash reference
Reference Manufacturer
M29W128GL70ZA6E NUMONYX
M29W128GH70ZA6E NUMONYX
S29GL128P90FFIR20 SPANSION
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