Obsolete Product(s) - Obsolete Product(s)
Horizontal Section
AN1290
12/62
STMicroelectronics Confidential
4.1.2
Digital Sync Detection
The H/HV sync pulse is detected on pin 1 by a comparator with hysteresis, compatible with the
standard TTL. It is intended for digital sync only (separate or composite). The IC synchronizes on
the pulse front edge. A pull-down resistor (200 k
Ω
) is included.
Sync polarity recognition is performed as follows: The comparator output controls the charge or
discharge of an internal 50pF capacitor with ±0.1µA current. Depending on the polarity of the sync
signal, the capacitor voltage will either drift towards the ground or the 8V supply. A comparison of
capacitor voltage with a 4V threshold indicates the sync polarity. The recognition delay is
approximately 2ms (typical) with a minimum value of 0.75 ms. This way, in the event of a Composite
sync signal, vertical sync pulses up to 0.75ms will not be unduly interpreted as a change in HSync
polarity.
Þ
Serration pulses: When they are missing, the inhibition of PLL1 during Vertical sync pulse
(described later) prevents any disturbance of the Horizontal oscillator. For this purpose, the
composite V pulse must be recognized within one horizontal half-period (see
4.1.3
Composite Sync
In order to extract the VSync pulse from the composite signal, the duration of each sync pulse is
compared with the horizontal period. As soon as the duration of a pulse exceeds 21% (minimum) of
the horizontal period (30% typical), this pulse is recognized as a VSync pulse.
The VSync duration measurement uses an internal capacitor and a current source that keeps a
constant ratio with Horizontal oscillator current source. Consequently, the system will work as
indicated only if the recommended value of 820 pF for oscillator capacitor Co is applied.
Otherwise for instance, when using a higher value, at the same frequency, all charge currents will be
higher and therefore the recognition delay will decrease possibly to less than 21% of the horizontal
period. This would lead to the incorrect detection of the Vertical Sync signal.
See
Section 9: I²C Control Section
for more information about sync management through I²C
programming.
4.1.4
Voltage-controlled Oscillator
The H oscillator is similar to the one in the TDA9109/9111. See
for the schematic diagram
and
for waveforms.
A voltage-follower stage imposes the same voltage on pin 8 as on pin 9, which is the PLL1 output.
The current in pin 8 is then fixed to:
Current mirroring provides two current sources, with values of 0.5 x I
8
(“source”) and 4 x I
8
(“sink”).
Two comparators with thresholds of respectively 1.6V and 6.4V control a toggle that switches ON or
OFF the 4 x I
8
current source.
Supposing this latter source is initially OFF, capacitor C
0
will charge at a rate:
until the 6.4V threshold is reached. At that moment, the 4 x I
8
current source is switched ON,
establishing a global discharge current equal to 3.5 x I
8
. Discharge will continue at a rate:
I
8
V
8
R
0
-------
=
dV
dt
-------
0.5xI
8
C
0
-----------------
=
dV
dt
-------
3.5xI
8
C
0
-----------------
=
