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AN1290 Horizontal

Section

4.1.8

PLL1 Inhibition

The PLL1 operation remains undisturbed if one (and only one) sync pulse front edge arrives in each
horizontal period, in phase with the V

φ

point on each sawtooth. In the event of a composite digital

sync pulse, this condition is no longer fulfilled during Vsync, when there are no serration pulses.

Figure 2: H Oscillator Waveform

6.4V

1.6V

V

0

5

5

D

u

ty

fac

tor

s

e

tt

in

g v

o

lt

age

10

12µs

V

Sync
pulse

V26

PLL2 Threshold

Range for PLL2

Forced OFF

Forced ON

Fly
back

t

st

φ

4V

«
...
13
14
15
16
17
...
»

Содержание TDA911 Series

Страница 1: ... will recognize all the functions and operation styles they are accustomed to use For low and medium range applications where certain sophisticated features are not required several different economical versions of the TDA9112 are available TDA9113 TDA9115 and TDA9116 Table 1 summarizes their respective features All versions are pin and software compatible with minor exceptions1 Recently the most ...

Страница 2: ...uty Factor ON OFF 16 4 1 11 Soft start 17 4 1 12 Output Stage 17 4 1 13 X ray Protection 17 4 1 14 Lock Unlock Detection 17 4 1 15 H Moire Cancellation 18 4 2 Application Hints 19 4 2 1 Minimizing Jitter 19 4 2 2 Output Stage 20 4 2 3 Enlarging the Frequency Range 21 4 2 4 X Ray Protection 22 Chapter 5 Vertical Section 23 5 1 Theory of Operation 23 5 1 1 Structure of V Section 23 5 1 2 Ramp Genera...

Страница 3: ...n Hints 42 6 2 1 E W Output Stage 42 Chapter 7 DC DC Converter Section 44 7 1 Structure of the DC DC Converter and B Loop 44 7 1 1 Structure of the Converter Section 44 7 1 2 External or Internal Sawtooth Configuration 44 7 1 3 B Output Polarity 45 7 1 4 Soft start 45 7 1 5 Selecting the Trigger Timing 46 7 1 6 Structure of the Regulation Loop Step up Current mode 46 7 1 7 Structure of the Regulat...

Страница 4: ... 4 62 STMicroelectronics Confidential 9 2 TDA9112 Family as I C Bus Device 55 9 3 Receiving Data 55 9 4 Sending Data 56 9 5 Register Organization 56 9 6 Management of Status Register and Sync Priority 58 Chapter 10 I C Bus Control Register Map 60 ...

Страница 5: ...red Smooth frequency transitions Internal soft start Vertical Constant amplitude self adaptive vertical ramp generator 50 to 185 Hz frequency range ON OFF Output function for Power Management I C control of V amplitude V position S and C correction amplitudes S correction adapted to normal or super flat tubes Lock Unlock data by I C except for the TDA9115 Signal for early V Blanking East West Pinc...

Страница 6: ...d negative H and V sync signals Accepts Composite sync signals with the automatic management of serration pulses Sync on Green is not extracted this function is available in ST Video preamps Vertical Moire compensation controlled by I C programming Horizontal Moire compensation I C programming may be optimized for combined or separate structure EHV Scanning TDA9112 9113 9116 self contained TDA9115...

Страница 7: ...n modified to fit in the tracking feature As a result it is possible to adjust amplitude or to switch between the VGA modes without impairing linearity The law of S correction has been modified allowing perfect fitting to various types of tubes Further to regular amplitude and centring settings which maintain ideal linearity and pincushion correction thanks to the tracking feature the new prescale...

Страница 8: ...ent threshold using pin 16 Isense previous 2V is convenient when implementing a sawtooth oscillator but the new value 1 2V same as in UC 384x family is better adapted for Isense as in current mode step up converters A new control bit performs the ON OFF function independently of Horizontal and with soft start In addition to the three possible phases for the DC DC converter HOut Up HOut Down after ...

Страница 9: ...istics Voltage on pin 9 is proportional to H Oscillator frequency 10 Should be filtered to HGND it improves H jitter by filtering the DC level for H position Capacitor on pin 10 also sets the time constant for soft start 11 Output pin for composite dynamic H V Focus or Brightness The waveform on this pin is the sum of two parabolas one at horizontal frequency one at vertical frequency The internal...

Страница 10: ...tion The middle value of this signal is 3 5 8 of the reference voltage pin 13 An equal voltage should be derived from pin 13 through a resistive divider to bias the Vertical booster positive input 24 Provides the complete waveform to control Horizontal amplitude including DC for H Size with EHV compensation Pincushion Keystone and symmetric Corner It has the structure of an Emitter follower a pull...

Страница 11: ...il the sync pulse coincides with an adjustable level on the sawtooth Changing the level is used to adjust the H position PLL2 adjusts the phase of the output stage compensating for the storage time of the H scanning transistor until the middle of the H flyback pulse coincides with a predetermined level on the sawtooth The horizontal phase and duty factor may be adjusted by I C programming Register...

Страница 12: ...s soon as the duration of a pulse exceeds 21 minimum of the horizontal period 30 typical this pulse is recognized as a VSync pulse The VSync duration measurement uses an internal capacitor and a current source that keeps a constant ratio with Horizontal oscillator current source Consequently the system will work as indicated only if the recommended value of 820 pF for oscillator capacitor Co is ap...

Страница 13: ...cillation frequency If the Vφ point on sawtooth arrives before the HSync pulse front edge the sink current is activated in the interval this will decrease the oscillation frequency when PLL1 is locked there is a very narrow source current pulse just before the Vφ point and a very narrow sink pulse just after therefore the voltage on pin 9 remains stable Vφ may be adjusted by 0 6V around the averag...

Страница 14: ...s to the other variables we have to consider a tolerance of 1 for R 5 or 10 for C and 6 for the numerical factor which incorporates a current ratio Consequently the free running frequency can vary from 12 or 17 of the designed value using safety margins can reduce the usable relative frequency range by 2 x 12 or 2 x 17 or 9 if you can afford a 2 capacitor An other consequence of the free running f...

Страница 15: ...e front edge arrives in each horizontal period in phase with the Vφ point on each sawtooth In the event of a composite digital sync pulse this condition is no longer fulfilled during Vsync when there are no serration pulses Figure 2 H Oscillator Waveform 6 4V 1 6V V 0 5 5 Duty factor setting voltage 10 12µs V Sync pulse V26 PLL2 Threshold Range for PLL2 Forced OFF Forced ON Fly back tst φ 4V ...

Страница 16: ...d to a secondary of the scanning transformer through a current limiting resistor In order to allow lower values of the limiting resistor and therefore faster transmission of the flyback data the maximum input current into this pin has been increased to 5 mA The reference point for PLL2 is the middle of the flyback pulse as seen on pin 12 PLL2 will manage to make it coincide with the 4V point on th...

Страница 17: ...eless and for other reasons we recommend keeping an AC coupling between pin 26 and the driver For more information refer to Section 4 2 2 Output Stage The output transistor is forced ON during the negative slope part of the sawtooth It is forced OFF during flyback as seen on pin 12 and this safety function has the priority over any other control The goal is to prevent the scanning transistor from ...

Страница 18: ...uly interpreted as a loss of locking Further to this indication as soon as an Unlock state is detected the oscillator frequency change rate is decreased When switching from High to Low frequency the B regulation loop will have enough time to decrease the B value accordingly thus preventing the destruction of the scanning transistor by overcurrent and overvoltage According to the typical applicatio...

Страница 19: ...d to HGND Then connect the low side end of PLL2 capacitor formerly grounded to the medium point of resistor bridge This way the compensation pulses will be applied to pin 5 through the capacitor The TDA9116 provides either internal or external compensation which is selected by I C programming Sad16h d3 2 When internal compensation is selected pin 11 becomes a 7 bit DAC with a span between 0 and 5 ...

Страница 20: ...These parasitic voltages appear in series with the capacitor and induce jitter they will be minimized if the loop IC pin capacitor IC ground presents the smallest possible area The loops that include resistors are less critical Nevertheless it is advisable to keep the connection to R0 as short and small as possible to minimize parasitic capacitance on pin 8 The loops emitting parasites obviously s...

Страница 21: ...o this pin should be avoided because it would give rise to high current spikes which may cause localized jitter By the way please notice in this schematic the AC coupling between IC output and driver stage The reason for this is that when the H output is inhibited for instance when the X ray protection is activated the driver stage is supposed to remain fully conductive This would lead to high cur...

Страница 22: ...ilter capacitor very close to the IC do not create a loop which may be influenced by a huge dI dt establish a path for the arcing current that does not cross the main chassis A well accepted disposition is as follows The ground connection from the outer conductive paint of the display tube should only go to the ground near the tube socket this way the charges stored inside the tube will not flow t...

Страница 23: ...Loop The structure of the complete ramp generator is represented in Figure 6 There are two different operating modes depending on whether a sync pulse is present When there is no sync pulse switch NoS No Sync is closed and switch S Sample is open Comparison voltage for discharging Co is set to 5V or more precisely to 5 8 of reference voltage Because 5V are forced on Cs current I o is null or very ...

Страница 24: ...very subsequent sync edge will trigger the sampling and then the discharge of C0 so that Cs always stores the previous sawtooth peak value V Cs is then converted to current I 0 by a high impedance converter using the following formula with R 18 kΩ Since Co is charged by I0 I 0 there is a feedback effect If the last sampled voltage was higher than 5V the charge current will decrease and conversely ...

Страница 25: ...sawtooth exceeds the 2 5V threshold defining a dead zone of 0 5 3 16 7 of the period In case the first detected edge proved incorrect i e a sync pulse back edge instead of the front edge the next discharge is triggered by the front edge regardless of the polarity of the sync pulse This mechanism fails if the sync pulse duration is too long hence the limit of 15 for V sync duty factor End of Vsync ...

Страница 26: ... in total charge current so that the next sampled voltage will be changed by where T vertical period If this value is higher than the initial V0 there will be permanent amplitude oscillation The condition for stability is then With internal values A 20 ts 13µs Rs 6kΩ R 18kΩ and recommended values Cs 470 nF and C0 150 nF this leads to T 29 3 ms 34 6 Hz Although this seems a comfortable safety margi...

Страница 27: ...ant regardless of the vertical frequency Figure 9 includes two multipliers First the vertical sawtooth referenced to its medium value 3 5V is converted to a current sawtooth with a null mean value and multiplied by the control current from the C correction I C DAC The control current may have positive as well as negative values in order to allow C correction in both directions Then the product is ...

Страница 28: ...od It would cause a fast transient at the beginning of the next vertical scanning and disturb the top of the screen For these reasons and before transmission to the following stages the exponential discharge waveform is removed from vertical sawtooth and replaced by a steep edge The signal is then maintained at a constant value until the rising of the positive slope as shown in Figure 10 After thi...

Страница 29: ...in Figure 11 The signal from ramp generator modified for the suppression of parasitic E W parabola is first sent to a variable gain amplifier for vertical amplitude setting then a variable offset is added for vertical position control The resulting Vramp is used to generate the S and C correction signals and further the E W corrections Since the corrections depend only on the present value of the ...

Страница 30: ...eo correspond to the center of the screen and end of the sawtooth to bottom of the screen At top of the screen there should be a black stripe corresponding to video blanking From that moment to preserve good linearity and geometry use only VPOS and VSIZE for final adjustments including for the various VGA modes 5 1 9 ON OFF Function A condition that disables H output namely supplying less than 8 5...

Страница 31: ...eases the scanning efficiency and the display dimensions both horizontal and vertical In all cases for a same scanning current display amplitude will increase almost proportionally to the beam current increase On the Vertical components the effect is much more visible in the second case than in the first one It has been named breathing because the whole display seems to inflate or deflate Since th...

Страница 32: ... and R4 by a same factor without affecting compensation Finally verify that pin 18 will always remain in the active range between 1 and 8V Here the ABL voltage appears at the common point of R1 and C1 the time constant for ABL is R1 x C1 Other circuitry like C2 R6 may be added to improve transient operation Usually the optimal compensation amount is not constant in relation to the H frequency For ...

Страница 33: ...ections Nevertheless biasing should be modified since the active range is now between 1 and 6 V The neutral point is 4 V when input is at 4 V changing the gain does not modify the amplitude For instance you can establish the resistive network to obtain 4 V for black display then adjust the gain only once to compensate the breathing with the white display Even if the 4 V bias is not accurate the nu...

Страница 34: ...s which are considered typical R1 12kΩ R5 R2 5 6kΩ R40a R40b 34 8kΩ R4 1Ω For all resistors except R4 preferably adopt 1 precision to have good centering If centering is defective and compensated by offset control linearity will suffer 5 2 2 Ripple Rejection With an improper layout the supply current of some other stage may create ripple between the local grounds and add parasites to the ramp sign...

Страница 35: ...r the capacitor discharge is triggered by the pulse and it stops when the capacitor voltage reaches the 2V lower threshold It may happen that the strong dI dt from a switching circuit located near the TDA9112 induces parasitic voltages in the loop constituted by the oscillator capacitor the IC and their connecting tracks In most cases these voltages which appear in series to the capacitor will hav...

Страница 36: ...4 Leakage on Cs Considering again the schematic of the AGC system and supposing that Cs has some leakage current Il the charges lost all along period T must be compensated during the sampling time t through Rs where VA is the voltage on Rs provided by the amplifier with gain A R1 R2 R1 If Vp is the peak sawtooth voltage we have VA Ax Vp and combining the two equations For instance at 50 Hz a 1 var...

Страница 37: ...ive slope Symmetric Corner not in the TDA9115 a 4th degree parabola positive or negative which will affect the corners of the display much more than the medium area The Corner correction may be adjusted independently at top and bottom of the display The TDA9112A provides additional features not represented on the block diagram The sensitivity and sign of EHT compensation may be adjusted through I ...

Страница 38: ...hat total HSize variation corresponding to the total variation of DC component be 17 of medium size Figure 16 Geometry and Focus TDA9112 One quadrant gain control Two quadrant gain control Dynamic 11 Keystone Side pincushion Side Pin Bal Out To Horizontal Phase Parallelogram Vdc 23 Vertical Ramp with amplitude control 3 35V E W Amp V Focus Brightness Amplitude H Focus Brightness Amplitude E W out ...

Страница 39: ...hen V9 5V tracking is not pursued above 5V to avoid a saturation of the output Under 5V they will remain proportional to V9 5 Remember that V9 is proportional to H frequency Þ The voltage on pin 24 corresponding to maximum amplitude minimum HSize voltage centre of the frame 8V on pin 17 is always the 2V plateau When Frequency tracking is selected when using a diode modulator the global E W signal ...

Страница 40: ...116 provide only the vertical parabola on pin 32 while pin 11 is devoted to Breathing compensation The TDA9112A provides all the features of the TDA9112 and in addition to these features on pin 11 Both signal polarities may be selected 1Fd1 either upwards concavity of the composite waveform with the apex at 2 1V or downwards concavity with the apex at 7V In order to best comply with the focus requ...

Страница 41: ...al class A amplifier this means that maximum amplitude will be reached at the end of H period which entails two drawbacks high dynamic range is needed and the more so because the TDA9112A allows a parabola with degree higher than 2 a high amplitude transient must take place to reach the low amplitude at beginning of next period This is a waste when it takes place during flyback i e while video is ...

Страница 42: ...imately 2V is available The peak value is approximately 8 5V with VAmp Breathing Pincushion Keystone and Corner corrections set to their maximum value We must choose the various resistors so that the output voltage will be approximately 0V when the input is 2V and will be at the maximum value when the input is 8 5V The maximum output is estimated at 40V for the maximum frequency to be compared wit...

Страница 43: ...d to the total E W voltage from IC mainly at a low H frequency when frequency tracking is used As a consequence it might be impossible to properly adjust the horizontal amplitude at a low frequency A convenient countermeasure is to implement a bias adjustment sub HSize with a DAC and a resistor 470kΩ should be convenient The adjustment is shown in Figure 17 ÞTake care to provide a pull down resist...

Страница 44: ...ing Sad01Fh d7 between 2V and 1 2V for switching OFF 1 2V is best suited for normal applications 2V for open loop converters The duty factor is not limited and can almost reach 100 Nevertheless after switching OFF the power MOS transistor will remain OFF for approximately 300 ns Compared to older circuits like the TDA9111 the DC DC section has been slightly modified to allow new applications like ...

Страница 45: ... to B pulse is possible which eliminates the need for a coupling transformer Still a negative going pulse is needed to make the MOS conductive For that reason B output pulse polarity may be programmed through I C Sad06h d7 Of course the converter Disable function will function regardless of the polarity i e it will either force output to LOW state if polarity is positive or to HIGH if the polarity...

Страница 46: ...has not yet been developed 7 1 6 Structure of the Regulation Loop Step up Current mode The voltage to be sensed may come either of the following sources Figure 18 from the EHV directly in this case a resistive divider is made with a bleeder resistor value approximately 500MΩ from the EHV and a fixed resistor approximately 100kΩ to ground This provides a feedback voltage approximately 4 8V or from ...

Страница 47: ... purpose and at high frequencies conduction should be triggered just after the end of the flyback period and the BoutPh value should be selected accordingly At lower frequencies you may choose to trigger with Hout down in order to avoid disturbance from parasitic voltages Nevertheless in this case dissipation in the power MOS transistor will tend to increase because switching will take place with ...

Страница 48: ...us paragraph In the TDA9112 only connecting pin 16 to a voltage higher than 6V for instance pin 13 automatically modifies the internal structure allowing an application such as the one shown in Figure 20 The DC voltage source is now in the 200V range higher than the highest needed B value A filtering cell L Cb is not really necessary Nevertheless because of the poor frequency response of the volta...

Страница 49: ... If the pulse duration is modulated by the E W signal the output voltage will be modulated accordingly The DC current sunk by the E W pin from pin 15 may be compensated for with a pull up resistor to pin 15 Minor changes from the TDA9111 DC DC section make the TDA9112 able to provide a constant duration pulse according to Figure 21 A P MOS high side switch has been represented controlled through c...

Страница 50: ...ites induced by DC DC Converter Timing Selection When using the Step down Voltage mode configuration there is no need to choose a timing since the current flow will automatically begin simultaneously with the HFocus ramp which is also used for comparison with the op amp output When using either Step up or Step down current mode at first glance triggering after flyback should be convenient Neverthe...

Страница 51: ...positive or negative between the end of a frame and the beginning of the next one as shown in Figure 22 To get the B scanning to follow this waveform it would be necessary to charge or discharge at a very high rate the Cb capacitor which proves difficult because the available current is limited Consequently it is mandatory to maintain the Cb value as low as possible possibly less than 1µF A limiti...

Страница 52: ...arly conduction of the scanning transistor Please refer to Figure 23 for a simplified logic diagram The following are not represented here but are already described in this Note Disable through X ray pin will be activated only 2 lines after the threshold has been exceeded in order to prevent incorrect triggering on very short parasitic voltages Soft start will take place every time when switching ...

Страница 53: ...rogramming Sad16h d0 Permanent blanking may be forced with 17d0 8 3 Application Hints 8 3 1 Using Inhibition Properly Emergency Procedure with H Lock V Blanking Inhibition through I C should be used with care for the following reason When horizontal scanning is inhibited B is inhibited at the same time Since scanning is stopped there is no more power consumption and B will keep its last value for ...

Страница 54: ...g signal may be present even when Locked An AC coupled transistor will provide an early negative going blanking pulse to be ORed with a blanking pulse from V flyback Still because of the AC coupling the display will be present when Unlocked important to display the OSD Figure 24 H Lock and V Early Blanking 14 15 B 220k 100k 47k TDA9112 H amp feedback 3 3 3 uF 12V Blank 0 1uF 100 22k ...

Страница 55: ...0 In the TDA9112 family all settings are programmed through the I C bus All ICs in the family are software compatible including the TDA9112A which uses more instructions Clock frequency may be as high as 400 kHz The duration of any pulse must be higher than 50ns because parasitic spikes are filtered with this time constant The input threshold for receiving data on pins 31 SDA and 30 SCL is 2 2 V t...

Страница 56: ... are default values forced during initial Reset Of course it is up to the user to load different values when starting for instance with the help of the Auto increment feature explained above Nevertheless the default values will always appear first Synchronization to Vertical The register contents sent to the TDA9112 are first latched they will be transferred only during the retrace of vertical osc...

Страница 57: ...bola on pin 32 will present an upward concavity 1 this VFocus parabola will present a downward concavity 16d0 1 HLock Unlock indication will be available on pin 3 added to VBlanking 0 VBlanking alone 16d1 1 PLL1 will be inhibited for the duration of extracted VSync necessary if serration pulses are absent 0 PLL1 will not be inhibited 16d2 1 charge pump current will be 1mA 0 charge pump current wil...

Страница 58: ...k 1Fd1 0 HVDyCor concavity of both H and V parabolas upwards 1 concavity downwards 1Fd2 0 Delay for detecting H Unlock same as the TDA9112 family 1 Delay divided by 2 1Fd3 When 17d2 HBOutEn is 0 disabled 0 HLock bit d7 of Read register is 1 similar to the TDA9112 family 1 HLock bit is 0 regardless of lock status When HBOutEn is 1 HLock bit monitors locking 0 if locked 1Fd4 0 All corrections on E W...

Страница 59: ...n d4 d3 the signs of those sync pulses which have been selected with 16d6 d5 1 negative or not detected 0 positive in d5 the status of X ray alarm 1 for Alarm ON Hout inhibited 0 Alarm OFF in d7d6 the Lock Unlock status of H and V oscillators 1 Unlocked 0 Locked Warning A d0 d1 or d2 at 1 just means that at least one sync pulse arrived since last SDetReset For obvious reasons Reset cannot be autom...

Страница 60: ...1 HPOS Horizontal Position 1 0 0 0 0 0 0 0 02 HMoiréMode 1 Separated 0 Combined HMOIRE Horizontal Moiré Amplitude 0 0 0 0 0 0 0 03 B SyncV 0 Asynchro BREF B reference 1 0 0 0 0 0 0 04 HDyCorTr 0 Not active HVDC HAMP HVDyCor horizontal amplitude 1 0 0 0 0 0 0 05 HDyCorPh 1 Middle 0 Start HVDC HPH HVDyCor horizontal phase 1 0 0 0 0 0 0 06 BOutPol 0 Type N HVDC VAMP HVDyCor vertical amplitude 1 0 0 0...

Страница 61: ...On VSyncSel 0 Comp 1 Sep SDetReset 0 No effect 1 Reset PLL1Pump 1 1 Fastest 0 0 Slowest PLL1InhEn 1 On HLockEn 1 On 17 TV 0 Off TH 0 Off TVM 0 Off THM 0 Off BOHEdge 0 Falling HBOutEn 0 Disable VOutEn 0 Disable BlankMode 1 Perm 18 Reserved 0 HVDC HSHAP HVDyCor Horizontal Shape 0 0 0 0 0 0 0 19 Reserved 0 EWSC East West S correction 1 0 0 0 0 0 0 1A Reserved 0 EWWC East West W correction 1 0 0 0 0 0...

Страница 62: ...f STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelec...

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