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STMicroelectronics Confidential
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AN1290 Horizontal
Section
until the 1.6V threshold is reached; then a new charge phase starts. As a result, the voltage on pin
6 will be a sawtooth with a (6.4-1.6)V amplitude and a period of:
Replacing I
8
by its value and taking the reverse, one obtains the theoretical formula:
If I
8
exceeds 1.5 mA, the oscillator components will not work in the optimal conditions; moreover, if
at the same time V
8
is higher than 6.2 V, there is a risk of saturation of internal circuitry. These two
reasons combined led to recommend R
0
> 4.2 k
Ω
.
Note:
All details relative to the oscillator waveform are represented in
with: Period = 12 µs,
Flyback duration = 3.2 µs, Duty factor = 50%, Sync pulse duration = 1 µs, Storage time = 2 µs.
4.1.5
PLL1
The aim of PLL1 is to control the oscillator's frequency and phase, until the front edge of the H sync
pulse just coincides with a determined (and adjustable) voltage (V
φ
) on the sawtooth.
Two current generators (one “source” and one “sink”) are connected to the PLL1 output (pin 9). This
pin is connected to an external low-pass filter, it controls pin 8 voltage through a voltage follower.
●
If the front edge of the HSync pulse arrives before the V
φ
point on sawtooth, the “source”
current is activated in the interval: this will increase the voltage and the oscillation frequency.
●
If the V
φ
point on sawtooth arrives before the HSync pulse front edge, the “sink” current is
activated in the interval, this will decrease the oscillation frequency;
●
when PLL1 is locked, there is a very narrow “source” current pulse just before the V
φ
point and
a very narrow “sink” pulse just after; therefore the voltage on pin 9 remains stable.
V
φ
may be adjusted by ±0.6V around the average value of 3.4V, through I²C programming (Register
01), allowing a control of the horizontal phase, up to ±10% of a period. For an optimum jitter, pin 10
should be filtered to GND (no limit on the capacitor value. It also sets the soft-start time constant).
The PLL1 capture range is large enough to synchronize with all incoming sync frequencies.
Normally, both “sink” and “source” currents should be set to 1mA, and the recommended
components in PLL filter are optimized accordingly. Nevertheless, the current value may be
switched to 0.3 mA by I²C programming (Sad16h/d3:2). Jitter may be improved by switching to
0.3 mA at low frequencies and to 1 mA at high frequencies. The default value is 0.3 mA.
In the TDA9112A there are four values for the current that can be selected by I²C programming
(Sad16h/d3:2).
4.1.6
Free-running Frequency and Range
When HSync pulses are absent or at low frequency, the PLL1 output will clamp to 1.33 V, which
corresponds to the free-run frequency (f
0
). From the formula for frequency, we get:
∆
T
h
C
0
x
∆
V
1
0.5xI
8
-----------------
1
3.5xI
8
-----------------
+
è
ø
æ
ö
è
ø
æ
ö
with
∆
V
6.4
1.6
–
4.8
=
=
=
f
h
V
8
2.286x R
0
x C
0
x
∆
V
(
)
(
)
-----------------------------------------------------------
V
8
10.97x R
0
xC
0
(
)
-------------------------------------------
=
=
f
0
1.33
10.97x R
0
xC
0
(
)
-------------------------------------------
0.1215
R
0
xC
0
-------------------
=
=
