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STMicroelectronics Confidential
approximately 4V when it is unlocked. The last elements are an internal comparator referenced to
6.25V (with hysteresis) and a CMOS inverter; you will find on its output pin 3 a HIGH state when
PLL1 is unlocked. The same data can also be read in the IC through the I²C bus. Nevertheless, a
Read request is necessary in this case.
There may be an ill-defined state and erratic pulses may appear during Lock
↔
Unlock transitions,
mainly when oscillator frequency approaches Lock state. The reasons for this are basic and cannot
be avoided. To prevent malfunctions, provide an external supplementary delay. Since the delay is
external, it can be made longer for the Unlocked
→
Locked transition (thus avoiding the parasitic
pulses), while being kept very short for the opposite Locked
→
Unlocked transition, when
emergency measures should be triggered in a short time.
Because some customers asked for a shorter reaction time to transition Locked
→
Unlocked, the
TDA9112A provides an option through I²C programming (Sad1Fh/d2) for a delay divided by two. Be
aware that as a consequence, a very long composite VSync signal without serration pulses could be
unduly interpreted as a loss of locking.
Further to this indication, as soon as an Unlock state is detected, the oscillator frequency change
rate is decreased. When switching from High to Low frequency, the B+ regulation loop will have
enough time to decrease the B+ value accordingly, thus preventing the destruction of the scanning
transistor by overcurrent and overvoltage. According to the typical application schematic, the
frequency will be reduced by approximately 0.1 kHz/ms.
Since pin 3 is also used for V blanking, levels on pin 3 are defined as follows:
●
approximately 0V: locked, not blanked
●
higher than 5V: unlocked
●
the blanking signal adds to Lock/Unlock level (+1V if Blanked).
The Lock/Unlock signal is available only if selected through I²C programming (Sad16h/d0).
4.1.15 H Moire Cancellation
The Moire phenomenon only takes place on color screens and when displaying grey areas resulting
from an alternation of black and white dots.
It may happen that the succession of black and white dots presents a pitch which is very close to
that of the TV screen. If in an area of the screen, the white dots fall exactly on the tube pixels, then,
at some further distance, they will fall exactly between the pixels. The result will be a succession of
bright and dark stripes with an approximately vertical direction. The nearer the dot pitch to the tube
Figure 3: Lock/Unlock
8V
I
SINK
I
SOURCE
To I²C
6.25V
0V = Lock
1V = Lock, Blank
5V = Unlock
6V = Unlock, Blank
3
