Figure 20.
Example of decoupling capacitor placed underneath
Via
Decoupling
capacitor
BGA ball
9.4
High speed signal layout
9.4.1
SDMMC bus interface
Interface connectivity
The SD/SDIO MMC card host interface (SDMMC) provides an interface between the AHB peripheral bus and
Multi Media Cards (MMCs), SD memory cards and SDIO cards. The SDMMC interface is a serial data bus
interface, that consists of a clock (CK), command signal (CMD) and 8 data lines (D[0:7]).
Interface signal layout guidelines
•
Reference the plane using GND or PWR (if PWR, add 10nf switching cap between PWR and GND).
•
Trace impedance: 50 Ω ± 10%.
•
All clock and data lines should have equal lengths to minimize any skew.
•
The maximum skew between data and clock should be less than 250 ps @ 10mm.
•
The maximum trace length should be less than 120 mm. If the signal trace exceeds this trace-length/speed
criteria, then a termination should be used.
•
The trace capacitance should not exceed 20 pF at 3.3 V and 15 pF at 1.8 V.
•
The maximum signal trace inductance should be less than 16 nH.
•
Use the recommended pull-up resistance for CMD and data signals to prevent the bus from floating.
•
The mismatch within data bus, data and CK or CK and CMD should be below 10mm.
•
All data signals must have the same number of vias.
Note:
The total capacitance of the SD memory card bus is the sum of the bus master capacitance C
HOST
, the bus
capacitance C
BUS
itself and the capacitance C
CARD
of each card connected to this line. The total bus
capacitance is C
L
= C
Host
+ C
Bus
+ N*C
Card
where the host is an STM32H723/33, STM32H725/35 and
STM32H730 microcontroller, the bus is all the signals and Card is SD card.
Figure 21. microSD card interconnection example
Figure 22. SD card interconnection example
show different
typical use cases
AN5419
High speed signal layout
AN5419
-
Rev 2
page 36/50