2.2.4
Analog voltage detector (AVD)
The AVD can be used to monitor V
DDA
power supply by comparing it to a threshold selected through the ALS[1:0]
bits of the PWR power control register (PWR_CR1). The threshold value can be configured to 1.7, 2.1, 2.5 or
2.8 V (refer to the
STM32H72x and STM32H73x datasheets
for the actual values).
The AVD is enabled by setting the AVDEN bit in PWR_CR1 register. An interrupt can be raised when V
DDA
goes
above or below the configured threshold.
2.2.5
System reset
A system reset sets all the registers to their default values except the reset flags in the clock controller RCC_RSR
register and the registers in the backup domain (see
).
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2.
Window watchdog end of count condition (WWDG reset)
3.
Independent watchdog end of count condition (IWDG reset)
4.
A software reset (Software reset)
5.
A low-power management reset.
Figure 9.
Reset circuit
VDD
Filter
Pulse generator
(20 µs min)
R
PU
OR
nreset (System Reset)
NRST
(External reset)
C
R
RCC
SFTRESET
lpwr_rst
wwdg1_out_rst
iwdg1_out_rst
pwr_por_rst
pwr_bor_rst
2.2.6
Bypass mode
The power management unit is configurable by software with the option to bypass. When bypassed, the core
power supply should be provided through VCAPx pins connected together.
In Bypass mode, the internal voltage scaling is not managed internally, and the external voltage value (1.0 to
1.35 V) must be consistent with the targeted maximum frequency (see the
STM32H72x and STM32H73x
datasheets
for the actual VOS level).
In Stop mode, it can be lowered to between 0.74 and 1.0 V (see datasheet for the actual SVOS level).
In Standby mode, the external source will be switched off and the V
CORE
domains powered down. The external
source will be switched on when exiting Standby mode.
In Bypass mode, the external voltage must be present before or at the same time as V
DD
. To avoid conflict with
the LDO, the external voltage must be kept above 1.15 V until the LDO is disabled by software.
AN5419
Reset and power supply supervisor
AN5419
-
Rev 2
page 17/50