4.1.2
Packages having Pxy_C but not the peer Pxy
On some packages, the peer Pxy_C and Pxy is not available, only the Pxy_C are.
As described above these pads give the best performance for the ADC.
To access to all the alternate functions of the conventional pad, the internal switch between the two peer pads
needs to be closed (PxySO bit).
In this way all the functionalities of the Pxy pad are available on the Pxy_C pad.
But there is an additional serial impedance due to this switch (300 Ω to 550 Ω) and additional parasitic
capacitance (2.5 pF) which may impact timing sensitive signals.
STM32CubeMX and the table “Port A and Port C alternate function” of the
STM32H72x and STM32H73x
datasheets
indicate the functions available on the Pxy_C pads by closing the switch between the two pads.
4.1.3
Package having Pxy available but nor the peer Pxy_C
Closing the switch in the pad (GPIOx_MODER bit) connects an ADC slow input to the Pxy pad (See Figure ADC
connectivity in the reference manual
STM32H723/733, STM32H725/735 and STM32H730 advanced Arm
®
-based
32-bit MCUs
(RM0468)). Also refer to the ADC
STM32H72x and STM32H73x datasheets
characteristic table
“Sampling rate for Slow channels”.
Another solution is to close the switch between the two peer pads (PxySO bit) instead of closing the switch in the
pad. In this way, an ADC fast input is connected to the Pxy pad. The performance is improved but will not
however be as high as for a package having a direct input from a Pxy_C pad. (see the
STM32H72x and
STM32H73x datasheets
ADC characteristic table “Sampling rate for Medium speed channels”)
AN5419
Analog inputs for ADC1, ADC2 and ADC3
AN5419
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Rev 2
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