Device operation
ST802RT1A, ST802RT1B
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Doc ID 17049 Rev 1
These two signals can be either driven by standard CMOS levels or by PECL levels. The
data coming from the optical transceiver are PECL signals and need to be converted to
CMOS level before being delivered to the data and clock recovery and then to the serial-to-
parallel interface to be transmitted to the digital portion.
7.20 PECL
transmitter
This circuit is designed to acquire the data coming from the parallel-to-serial interface and
NRZ-to-NRZI converter, and to transmit it to the optical transceiver. In this case, the data is
received by the transmitter in a CMOS format and is transmitted to the optical portion in a
PECL format. See
Figure 8
for the definition of PECL levels.
Table 32.
Configuration of signal detect voltage levels
SDn
SDp
Mode
Ground
Ground
TX mode
Ground
Positive voltage
Undefined state
Voltage>0.6
Voltage>0.6
Undefined state
PECL
LOW
(PECL
MID
)
PECL
LOW
FX mode asserted, but no data valid on the line
PECL
HIGH
(PECL
MID
)
PECL
LOW
FX mode asserted, but no data valid on the line
PECL
HIGH
PECL
HIGH
Undefined state
PECL
LOW
(PECL
MID
)
PECL
HIGH
FX mode asserted, link OK and data valid
Figure 8.
PECL levels
