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5.1 Circuit Descriptions
5 – 3
5.1.4
Proportional–Integral–Derivative
The resulting amplified error signal
P
×
ε
(inverted at this point) is
then distributed to the three paths,
P
,
I
, and
D
(see schematic page
6). The
P
path is unchanged, while the other two paths,
I
and
D
,
each use 12-bit DACs (U606A and U606B) for vernier attenuation of
the
I
and
D
gains.
Integral action is achieved using a multiplexed feedback capacitor
design. U602 is addressed to choose one of four capactors, all of
which are parallel to the fixed feedback capacitor C643, whose small
capacitance sets the maximum integral gain value. A similar switch-
ing method is employed in the derivative path to choose the input
capacitance of the di
ff
erentiating amplifier U609B. Note R617, which
limits the maximum derivative gain to just over
+
40 dB.
Each of the three signal paths,
P
,
I
and
D
, passes through an analog
switch (U601A, U601B, and U601C, respectively) before being com-
bined at the summing junction, the inverting input of op-amp U605B.
These switches allow individual signals (
P
,
I
or
D
) to be switched on
or o
ff
at the summing junction. Manual o
ff
set control also enters the
summing junction, though no switch is used since zeroing the o
ff
-
set circuit (U610 with U611) is equivalent to switching out the o
ff
set
signal. Note that R643 is placed in series with the feedback resistor
R615 in order to roughly match the switch resistance of each of the
switches in U601.
5.1.5
Output Circuitry
U807 is used to switch the ouput of the SIM960 between Manual
and PID modes. The signal then passes through two cascaded diode
limiter circuits.
D801 and D802 clamp the output signal with respect to the upper
limit voltage generated by U508A, together with U509B and U509C.
The e
ff
ect of cascading two diode limiter circuits is to narrow the
clamping range by roughly a factor of two, down to about 100 mV.
Comparator U805 switches high when the output signal (going into
the limiter circuit at R823) exceeds the upper limit voltage. The in-
verting input of U805 is referenced to the upper limit voltage through
the divider combination R844 and R845, e
ff
ectively shifting the sat-
uration turn-on location with respect to the clamping “knee”. The
lower limit clamp is similarly implemented by D803 and D804.
The output of the limiter circuit is bu
ff
ered by a composite amplifier
consisting of U821 and U822. This arrangement provides the driving
capability of the LT1010 without su
ff
ering its large input o
ff
set volt-
age, since the output of U822 is servoed to the noninverting input to
SIM960 Analog PID Controller
Содержание SIM960
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