Spirent DLS 6700, Руководство по эксплуатации

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DLS 6700 Operating Manual
Page 4-10 7104000557 Spirent Communications
bit 6: MSS/RQS (Master Summary Status/Request Service)
MSS is raised when either MAV or ESB are raised and enabled. MSS
summarizes all the status bits of the DLS 6700, as defined by the
IEEE 488.2 standard.
bits 7, 3, 2, 1, 0
These bits are not used by the DLS 6700.
4.6.2 Event Status Register (ESR)
The Event Status Register monitors events within the system and reports on those
enabled. It records transitory events as well. The DLS 6700 implements only the
IEEE 488.2 Standard Event Status Register (ESR). It is defined as:
bit 0 Operation Complete. This bit is set in response to the *OPC command when
the current operation is complete.
bit 1 Request Control. The DLS 6700 does not have an IEEE 488 bus, and so this bit
is always 0.
bit 2 Query Error. There was an attempt to read an empty output queue or there
was an output queue overflow (maximum output queue capacity is 75 bytes).
bit 3 Device Dependent Error. This error bit is set when the DLS 6700 receives a
command to set the length of a fixed loop. Only variable loops can have their
length changed.
bit 4 Execution Error. The data associated with a command was out of range.
bit 5 Command Error. Either a syntax error (order of command words) or a seman-
tic error (spelling of command words) has occurred. A GET (Group Execute
Trigger) or *TRG command will also set this bit.
bit 6 User Request. Indicates that the user has activated a Device Defined control
through the front panel. Not used, so this bit is always 0.
bit 7 Power on. This bit is set when the DLS 6700 is turned on. Sending *ESR?
clears the bit and it stays clear until the power is turned on again.
The setting of the Event Status Register can be read with the Event Status Register
query command (*ESR?). This will put the value of the register in the output queue,
AND will clear the register.