Spectrum M2i.3010, Руководство по оборудованию

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Trigger modes and appendant registers Trigger masks
(c) Spectrum GmbH 91
Trigger AND mask
The purpose of this passage is to explain the trigger AND mask (see left figure) and all the appendant software
registers in detail.
The AND mask shown in the overview before as one object, is separated into two parts: a general AND mask
for external TTL trigger and software trigger and a channel AND mask.
Every trigger source of the M2i series cards
except the software trigger is wired to one of the above mentioned AND
masks. The user then can program which trigger source will be recognized,
and which one won’t.
This selection for the general mask is realized with the SPC_TRIG_ANDMASK
register in combination with constants for every possible trigger source.
This selection for the channel mask is realized with the
SPC_TRIG_CH_ANDMASK0 and the SPC_TRIG_CH_ANDMASK1 register
in combination with constants for every possible channel trigger source. In
either case the sources are coded as a bitfield, so that they can be combined
by one access to the driver with the help of a bitwise OR.
The table below shows the relating register for the general AND mask and
the possible constants that can be written to it.
The following example shows, how to setup the AND mask, for an external TTL trigger. As an example a simple level detection has been
chosen. The explanation and a detailed description of the different trigger modes for the external TTL trigger inputs will be shown in the ded-
icated passage within this chapter.
The table below is showing the constants for the channel AND mask and all the constants for the different channels.
The following example shows how to setup the
AND
mask, for a channel trigger. As an example a simple level detection has been chosen.
The explanation and a detailed description of the different trigger modes for the channel trigger will be shown in the dedicated passage
within this chapter.
Register Value Direction Description
SPC_TRIG_AVAILANDMASK 40420 read Bitmask, in which all bits of the below mentioned sources for the AND mask are set, if available.
SPC_TRIG_ANDMASK 40430 read/write Defines the events included within the trigger AND mask of the card.
SPC_TMASK_EXT0 2h Enables the external trigger0 for the AND mask. The card will trigger when the programmed condition for this input is
valid.
SPC_TMASK_EXT1 4h Enables the external trigger1 for the AND mask. This input is only available on digital cards. The card will trigger
when the programmed condition for this input is valid.
SPC_TMASK_XIO0 100h Enables the extra TTL trigger 0 for the AND mask. On plain cards this input is only available if the option BaseXIO is
installed. As part of the digitizerNETBOX this input is available as connector Trigger B.
SPC_TMASK_XIO1 200h Enables the extra TTL trigger 1 for the AND mask. This input is only available ift the option BaseXIO is installed.
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_ANDMASK, SPC_TMASK_EXT0); // Enable external trigger within the AND mask
spcm_dwSetParam_i32 (hDrv,SPC_TRIG_EXT0_MODE, SPC_TM_HIGH ); // Setting up external TTL trigger for HIGH level
Register Value Direction Description
SPC_TRIG_CH_AVAILANDASK0 40470 read Bitmask, in which all bits of the below mentioned sources/channels (0…31) for the channel AND
mask are set, if available.
SPC_TRIG_CH_AVAILANDMASK1 40471 read Bitmask, in which all bits of the below mentioned sources/ channels (32…63) for the channel AND
mask are set, if available.
SPC_TRIG_CH_ANDMASK0 40480 read/write Includes the analog or digital channels (0…31) within the channel trigger AND mask of the card.
SPC_TRIG_CH_ANDRMASK1 40481 read/write Includes the analog or digital channels (32…63) within the channel trigger AND mask of the card.
SPC_TMASK0_CH0 1h Enables channel0 (channel32) for recognition within the channel AND mask.
SPC_TMASK0_CH1 2h Enables channel1 (channel33) for recognition within the channel AND mask.
SPC_TMASK0_CH2 4h Enables channel2 (channel34) for recognition within the channel AND mask.
SPC_TMASK0_CH3 8h Enables channel3 (channel35) for recognition within the channel AND mask.
… … …
SPC_TMASK0_CH28 10000000h Enables channel28 (channel60) for recognition within the channel AND mask.
SPC_TMASK0_CH29 20000000h Enables channel29 (channel61 for recognition within the channel AND mask.
SPC_TMASK0_CH30 40000000h Enables channel30 (channel62) for recognition within the channel AND mask.
SPC_TMASK0_CH31 80000000h Enables channel31 (channel63) for recognition within the channel AND mask.
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_CH_ANDMASK0, SPC_TMASK_CH0); // Enable channel0 trigger within the AND mask
spcm_dwSetParam_i32 (hDrv,SPC_TRIG_CH0_MODE, SPC_TM_HIGH ); // Setting up ch0 trigger for HIGH levels