4-4
Chapter 4: Channel Configuration, Data, and Status
User’s Manual Pub. 0300181-07 Rev. A
Reset Flags: (Configuration Bit 2)
The reset flags command is performed when this bit is set. Reset flags affects the
counter zero, counter limit and counter maximum flags (Status word bits 8, 6,
and 5, respectively.) These particular flags remain high, regardless of the counter
behavior, until a reset is performed. This allows adequate time to read the flags
after an event has occurred.
•
If user Counter Limit is set to 0 (0 indicates undefined), these flags will
remain high until reset:
-
Count is equal to zero or counter decremented down through zero
flag (Status word bit 8).
-
Count up or down through the maximum count flag (Status word bit
5).
•
If a Counter Limit is never set (Status word bit 6) the flags will not
annunciate.
•
If user Counter Limit is set to a non-zero value ( User defined limit),
these flags will remain high until reset:
-
Count is equal to zero or counter decremented down through zero
flag (Status word bit 8).
-
Count up or down through the limit flag (Status word bit 6).
•
And these flags do not remain high:
-
Maximum count flag (Status word bit 5) is set if count value is
exactly equal to 32,767 (16 bit) or 8,388,607 (24 bit).
-
Otherwise, it is clear.
Rate Mode: (Configuration Bit 3)
Refer to Appendix A for Floating Point Rate Mode
Rate - Average:
When the rate mode bit is set to a “1” the rate detection circuit is in “Rate
Average” mode. The rate average mode counts the number of input transitions
over a 1 second interval and calculates the input rate averaged over the 1 second
interval. The rate average mode is slow, in that it reports updated rates at once
per second. However, this mode is accurate to ± 1 count over the full range of
measurement.
Figure 4-4. One-Second Rate Average
Rate - Instant:
When this bit is reset to “0” the rate detection circuit operates in “Instant” mode.
Instant measurements are fast, in that they calculate a rate based on one cycle.
However, the accuracy of the measurement degrades as the input clock rate goes
up to 50KHz, and any jitter within one cycle will be measured.
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