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34
PRS-500
Pin No.
Pin Name
I/O
Description
D3
SD_DAT1
I/O
Not used (Open)
D4
ETHERINT
I
Not used (Fixed to “H”)
D5
NVDD1
—
2.9V DC input
D6
USBD_VP
I
USB plus input
D7
QVDD4
—
1.95V DC input
D8
UART2_TXD
O
Not used
D9
NVDD3
—
2.9V DC input
D10
NAND
-
ALE
O
Address latch enable for NAND Flash ROM
D11
PCUSB
O
Power controll output for USB
D12
PCAUDIO
O
Power controll output for DAC clock
D13
SRMS
O
Reset output for MS controller
D14
AMUTE
—
Not used (Open)
D15
SRDSP
O
Reset output for DAC
E1
A21
O
25 bits address bus
E2
A22
O
25 bits address bus
E3
D30
I/O
32 bits data bus
E4
D29
I/O
32 bits data bus
E5
NVDD1
—
2.9V DC input
E6
QVSS
—
Ground
E7
UART2_RTS
I
Not used (Fixed to “H”)
E8
UART1_RXD
I
Serial data input from sub CPU
E9
UART1_CTS
O
Serial clear for sub CPU
E10
NAND
-
CLE
O
Command latch enable for NAND Flash ROM
E11
USB_CHG
O
USB charge controll output
E12
SREINK
O
Reset output for indicator controller
E13
NMI
I
Not used (Fixed to “H”)
E14
ED0
I/O
8 bits data bus for indicator
E15
PA3
—
Not used (Open)
F1
A20
O
25 bits address bus
F2
A19
O
25 bits address bus
F3
D28
I/O
32 bits data bus
F4
D27
I/O
32 bits data bus
F5
NVDD1
—
2.9V DC input
F6
NVDD1
—
2.9V DC input
F7
UART2_CTS
O
Not used (Fixed to “L”)
F8
SSI_RXCLK
I
Not used (Open)
F9
SSI_TXDAT
O
Serial audio data output for audio DAC
F10
PD8
—
Not used (Open)
F11
QVDD3
—
1.95V DC input
F12
SRSD
O
Reset output for SD controller
F13
MSDET
I
MS detect input from MS slot
F14
ED2
I/O
8 bits data bus for indicator
F15
ED4
I/O
8 bits data bus for indicator
G1
A17
O
25 bits address bus
G2
A18
O
25 bits address bus
G3
D26
I/O
32 bits data bus
G4
D25
I/O
32 bits data bus
G5
NVDD1
—
2.9V DC input
G6
NVSS
—
Ground