Sony MXD-D400 Operating Instructions (primary manual), Руководство по обслуживанию

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MXD-D400
•
MAIN BOARD IC12 M30624MGN-A23FP (MD MECHANISM CONTROLLER)
Pin No. Pin Name I/O Description
1 FLDT O
Display serial data output terminal Not used
2 FLCK O
Display serial data transfer clock signal output terminal Not used
3 LEVEL-L O
L-channel level output to the system controller
4 LEVEL-R O
R-channel level output to the system controller
5 to 7 OPEN
— Not used
8 BYTE I
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
9 CNVSS
— Ground terminal
10 XIN-T
I Sub system clock input terminal (32.768 kHz)
11 XOUT-T
O Sub system clock output terminal (32.768 kHz)
12 SRST I
System reset signal input from the system controller and regulator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13 XOUT
O Main system clock output terminal (10 MHz)
14 GND
— Ground terminal
15 XIN
I Main system clock input terminal (10 MHz)
16 VCC
— Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal (fixed at “H” in this set)
18 DQSY I
Digital In U-bit CD format subcode Q sync (SCOR) input from the MD DSP
“L” is input every 13.3 msec Almost all, “H” is input
19 PDOWN
I Power down detection signal input terminal “L”: power down, normally: “H”
20 SQSY I
Subcode Q sync (SCOR) input from the MD DSP
“L” is input every 13.3 msec Almost all, “H” is input
21
KBCLK O Not used
22 KBDATA O Not used
23 IICBUSY O Busy signal output for the I2C bus “L” active Not used
24 A1OUT — Not used
25 XINT I Interrupt status input from the MD DSP
26 BEEP O Beep sound drive signal output terminal Not used
27 XELT O Not used
28 IICPOWER O Not used
29 IICCLK I IIC data transfer clock signal input from the system controller
30 IICDATA I/O IIC data bus with the system controller
31 SWDT O Writing data output to the MD DSP
32 SRDT I Reading data input from the MD DSP
33 SCLK O Serial clock signal output to the MD DSP
34 KBCLKCTL O Not used
35 L3DATAO O L3 bus data output terminal Not used
36 L3DATAI I L3 bus data input terminal Not used
37 L3CLK O L3 bus data transfer clock signal output terminal Not used
38 L3MODE O L3 bus mode control signal output terminal Not used
39 ADARST O System reset signal output terminal Not used
40 ADALATCH O Serial data latch pulse output terminal Not used
41 EPM I Not used
42 OCLIPSEL O Not used
43 OPEN — Not used
44 PROTECT I
Detection input from the disc reflection rate detect switch
“L”: high reflection rate disc, “H”: low reflection rate disc
45 SCL (EEP) O Serial clock signal output to the EEPROM